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ics for communications isdn echocancellation circuit for terminal applications iec-q te psb 21911 version 5.2 psf 21911 version 5.2 data sheet 11.97 ds 1
psb 21911 revision history: original version: 11.97 previous releases: none page subjects (changes since last revision) for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide: see our webpage at http://www.siemens.de/semiconductor/address/address.htm. edition 11.97 published by siemens ag, hl ts, balanstra?e 73, 81541 mnchen ? siemens ag 28.11.97. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the semiconductor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered.
psb 21911 psf 21911 table of contents page semiconductor group 3 11.97 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 1.2 logic symbol p mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 1.3 logic symbol stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 1.4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 1.5 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 1.6 microprocessor bus interface (overview) . . . . . . . . . . . . . . . . . . . . . . . . .21 1.7 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.7.1 isdn pc adapter card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.7.2 isdn stand-alone terminal with pots interface . . . . . . . . . . . . . . . . . . .23 1.7.3 isdn feature phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1.7.4 isdn-modem pc card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.1 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 2.2 device architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 2.3 iom-2 interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.3.1 iom-2 frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2.3.2 iom-2 command / indication channels . . . . . . . . . . . . . . . . . . . . . . . . . .34 2.3.3 iom-2 monitor channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 2.3.4 activation/deactivation of iom-2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . .37 2.3.5 superframe marker . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.3.6 iom-2 output driver selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 2.4 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.4.1 microprocessor clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.4.2 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 2.5 u-transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 2.5.1 u-frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 2.5.2 eoc-processor and mon-0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 2.5.3 maintenance (mon-1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 2.5.4 overhead bits (mon-2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 2.5.5 local functions (mon-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 2.5.6 state machine notation rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 2.5.7 state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 2.5.8 c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 2.5.9 layer 1 loop-backs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 2.5.10 analog line port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 2.6 access to iom-2 channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .81 2.6.1 b-channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 2.6.2 d-channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 2.6.3 c/i channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 2.6.4 monitor channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 2.7 s/g bit and bac bit in te mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89
psb 21911 psf 21911 semiconductor group 4 11.97 2.7.1 applications with elic on the linecard (pbx) . . . . . . . . . . . . . . . . . . . . .90 2.8 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 2.9 power controller interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 3 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 3.1 c/i channel programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 3.2 monitor channel programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 3.3 layer 1 activation/deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 3.4 external circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 3.4.1 power supply blocking recommendation . . . . . . . . . . . . . . . . . . . . . . . .109 3.4.2 u-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110 3.4.3 oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 4 register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 4.1 interrupt structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114 4.1.1 monitor-channel interrupt logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 5.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 5.2 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 5.3 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 5.4 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 5.4.1 parallel microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . .136 5.4.2 serial microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . .140 5.4.3 iom-2 interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .142 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 7 external component sourcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 8 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 appendix app a jitter on iom-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 app b s/g bit control state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 app c quick reference guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 index iom ? , iom ? -1, iom ? -2, sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, epic ? -1, epic ? -s, elic ? , ipat ? -2, itac ? , isac ? -s, isac ? -s te, isac ? -p, isac ? -p te, idec ? , sicat ? , octat ? -p, quat ? -s are registered trademarks of siemens ag. musac ? -a, falc ? 54, iwe ? , sare ? , utpt ? , asm ? , asp ? , digitape ? are trademarks of siemens ag. purchase of siemens i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c-system provided the system conforms to the i 2 c specifications defined by philips. copyright philips 1983.
psb 21911 psf 21911 list of figures page semiconductor group 5 11.97 figure 1: stand-alone mode (left) and p mode (right). . . . . . . . . . . . . . . . . . . . . . . 8 figure 2: logic symbol p mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 3: logic symbol stand-alone mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 4: pin configuration p-lcc-44 and t-qfp-64 package (top view) . . . . . . . 12 figure 5: isdn pc adapter card. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 figure 6: isdn stand-alone terminal with pots interface . . . . . . . . . . . . . . . . . . 23 figure 7: isdn feature phone . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 8: isdn-modem pc card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 9: iec-q te device architecture (p mode) . . . . . . . . . . . . . . . . . . . . . . . . 28 figure 10: iec-q te device architecture (stand-alone mode). . . . . . . . . . . . . . . . . 29 figure 11: iom-2 clocks and data lines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 12: basic channel structure of iom-2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 13: definition of the iom-2 frame in te mode. . . . . . . . . . . . . . . . . . . . . . . . 32 figure 14: definition of the iom-2 frame in nt mode. . . . . . . . . . . . . . . . . . . . . . . . 33 figure 15: deactivation of the iom-2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 16: u-transceiver block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 17: crc-process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 18: block error counter test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 19: scrambler / descrambler algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 figure 20: eoc-processor: auto mode, transparent mode . . . . . . . . . . . . . . . . . . . 51 figure 21: state diagram notation u-transceiver. . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 22: state transition diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 23: test loop-backs supported by the iec-q te . . . . . . . . . . . . . . . . . . . . . 76 figure 24: dac-output for a single pulse. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 figure 25: pulse mask for a single positive pulse . . . . . . . . . . . . . . . . . . . . . . . . . . 80 figure 26: access to iom-2 channels (p mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 figure 27: procedure for the d-channel processing. . . . . . . . . . . . . . . . . . . . . . . . . 83 figure 28: c/i channel access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 figure 29: monitor channel access directions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 30: monitor channel protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 31: d-channel request by the terminal . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 figure 32: reset sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 figure 33: sampling of interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 34: example: c/i-channel use (all data values hexadecimal) . . . . . . . . . . . . 97 figure 35: complete activation initiated by lt . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 36: complete activation initiated by te . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 37: complete deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 38: u only activation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 39: lt initiated activation with u-interface active . . . . . . . . . . . . . . . . . . . . 105 figure 40: te-activation with u active and exchange control (case 1) . . . . . . . . . 106 figure 41: te-activation with u active and no exchange control (case 2). . . . . . . 107 figure 42: deactivation of s/t only. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
psb 21911 psf 21911 semiconductor group 6 11.97 figure 43: power supply blocking. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 figure 44: u-interface hybrid circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 45: crystal oscillator or external clock source . . . . . . . . . . . . . . . . . . . . . . 111 figure 46: interrupt structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 figure 47: test condition for maximum input current. . . . . . . . . . . . . . . . . . . . . . . 131 figure 48: u-transceiver input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 figure 49: maximum sinusoidal ripple on supply voltage . . . . . . . . . . . . . . . . . . . 135 figure 50: input/output waveform for ac tests . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 51: siemens/intel read cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 figure 52: siemens/intel write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 figure 53: siemens/intel multiplexed address timing. . . . . . . . . . . . . . . . . . . . . . . 137 figure 54: siemens/intel non-multiplexed address timing. . . . . . . . . . . . . . . . . . . 137 figure 55: motorola read timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 56: motorola write cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 figure 57: motorola non-multiplexed address timing. . . . . . . . . . . . . . . . . . . . . . . 138 figure 58: serial p interface mode write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 59: serial p interface mode read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 60: iom-2 timing in nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 figure 61: dynamic characteristics of power controller write access . . . . . . . . . . 144 figure 62: dynamic characteristics of power controller read access . . . . . . . . . . 144 figure 63: reset signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 figure 64: s/g bit state machine notation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 figure 65: state machine (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 figure 66: state machine (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 figure 67: state machine (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 figure 68: u-transceiver state diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
psb 21911 psf 21911 list of tables page semiconductor group 7 11.97 table 1: microprocessor bus interface. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 table 2: modes of operation (p and stand-alone mode) . . . . . . . . . . . . . . . . . . .26 table 3: test modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 4: dout driver modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 table 5: microprocessor interface modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 table 6: u-frame structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 table 7: eoc-codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 table 8: executed eoc commands in auto mode . . . . . . . . . . . . . . . . . . . . . . . . .53 table 9: mon-1 s/q-channel commands and indications . . . . . . . . . . . . . . . . . . . .54 table 10: mon-1 m-bit commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 table 11: mon-2 structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 12: control of overhead bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 table 13: mon-8 local function commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 table 14: timers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 table 15: u-transceiver c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 table 16: b1/b2-channel data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 17: d-channel data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 table 18: s/g processing mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .89 table 19: control structure of the s/g bit and of the d-channel . . . . . . . . . . . . . . .90 table 20: reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 table 21: mon-8 and c/i-commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 table 22: u-interface signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100 table 23: register address map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 table 24: register summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 table 25: timing characteristics (serial p interface mode) . . . . . . . . . . . . . . . . . .141 table 26: iom-2 in nt mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143 table 27: power controller interface dynamic characteristics . . . . . . . . . . . . . . . .145 table 28: reset timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 table 29: u-transformer information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 table 30: crystal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 table 31: state machine input signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 table 32: state machine output signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .159 table 33: u-transceiver c/i codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162
semiconductor group 8 11.97 psb 21911 psf 21911 overview 1 overview the psb 21911, iec-q te version 5.2, is a specific derivative of the peb 2091, iec-q for terminal and small pbx applications. it features all necessary functions required for nts and terminal applications like pc add-on cards and terminal adapters. in stand-alone mode the psb 21911 iec-q te version 5.2 can be used fully pin compatible to iec-q v4.4 and former versions. in p mode it offers a parallel or serial microprocessor interface. the p rocessor i nterface (pi) of the iec-q te v 5.2 establishes the access of a microprocessor between u-interface and iom-2. its main function is illustrated in figure 1 . figure 1 stand-alone mode (left) and p mode (right) in p mode b channels, d channel, c/i codes and monitor commands can either be passed between the u-transceiver and iom-2 directly, or they can be looped through the p via the pi. any selection of "passed" or "looped" channels can be programmed via a control register. the p-interface mode is enabled by setting the pin pmode to "1". this pin was not to be connected in older versions of the iec-q. its internal pull down resistor selects the stand-alone mode, if the pin is left open. in stand-alone mode the iec-q te is controlled exclusively via the iom-2 interface and mode selection pins. its10193 fsc pi u u r iom -2 r iom -2
p-lcc-44 t-qfp-64 isdn echocancellation circuit for terminal applications iec-q te psb 21911 semiconductor group 9 11.97 version 5.2 cmos 1.1 features ? isdn u-transceiver with iom-2 and optional micro- processor interface ? compatible to nt modes and te mode of peb 2091 iec-q v5.1 ? perfectly suited for terminal and ta applications ? u-interface (2b1q) conform to ansi t1.601, etsi etr 080 and cnet st/laa/elr/dnp/822: C meets all transmission requirements on all ansi, etsi and cnet loops with margin C conform to british telecoms rc7355e C compliant with etsi 10ms micro interruptions ? iom-2 interface for connection of e.g. isac-s, sicofi-2/4te, arcofi, itac, hscx-te, isar, ipac, 3pac ? pin compatible to version 4.4 in the p-lcc-44 package in p mode: ? parallel or serial microprocessor interface and watchdog ? p access to b-channels, d-channel and intercommunication channels ? p access to iom-2 monitor-channels and c/i-channels ? adjustable microcontroller clock source between 0.96mhz and 7.68mhz ? selection between bit clock (bcl) and data clock (dcl) ? supports synchronization of basestations in cordless applications (e.g. ritl) ? supports d-channel arbitration with elic linecard (e.g. pbx) in all modes: ? single 5 volt power supply ? low power cmos technology with power down mode
psb 21911 psf 21911 logic symbol p mode semiconductor group 10 11.97 1.2 logic symbol p mode figure 2 logic symbol p mode
psb 21911 psf 21911 logic symbol stand-alone mode semiconductor group 11 11.97 1.3 logic symbol stand-alone mode figure 3 logic symbol stand-alone mode
psb 21911 psf 21911 pin configuration semiconductor group 12 11.97 1.4 pin configuration figure 4 pin configuration p-lcc-44 and t-qfp-64 package (top view) itp10290 psb 21911 iec-q te 123456 40 41 42 43 44 7 8 9 10 11 12 13 14 15 16 17 24 25 26 27 28 23 22 21 20 19 18 29 30 31 32 33 34 35 36 37 38 39 tp fsc dcl cls a3/ms0 ds/rd/mto cdout/a2/ms1 cdin/a1/ms2 mclk/diss d6/ad6/pca1 d5/ad5/pca0 xout xin pmode bin ain gnda2 dod/wr/r/w res dout din gndd/d7/ad7 gndd/a0/smode gndd ps2 ps1 tp1/cclk/ale int/int auto/rst aout gnda1 bout cs/tsp ad0/d0/pcd0 ad1/d1/pcd1 ad2/d2/pcd2 ad3/d3/pcrd ad4/d4/pcwr v ddd ddd v v dda1 dda1 v ref v v dda2 itp10217 mclk/diss d5/ad5/pca0 d6/ad6/pca1 cdin/a1/ms2 cdout/a2/ms1 a3/ms0 dcl fsc tp ps1 gndd auto/rst int/int tp1/cclk/ale ps2 gndd/a0/smode gndd/d7/ad7 din dout res ain bin n.c. xin pmode dda1 v n.c. n.c. n.c. gnda2 n.c. v ddd aout gnda1 bout ad0/d0/pcd0 ad1/d1/pcd1 ad2/d2/pcd2 ad3/d3/pcrd 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 33 34 35 36 37 38 39 40 41 42 43 44 45 46 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 16 15 14 13 12 11 10 9 8 7 6 5 4 3 32 dod/wr/r/w n.c. 48 47 64 2 1 ad4/d4/pcwr n.c. n.c. n.c. ddd v cs/tsp v ddd n.c. v dda1 xout v ref v dda2 n.c. n.c. n.c. n.c. n.c. n.c. cls n.c. ds/rd/mto n.c. n.c. iec-q te psb 21911
psb 21911 psf 21911 pin definitions and functions semiconductor group 13 11.97 1.5 pin definitions and functions the following tables group the pins according to their functions. they include pin name, pin number, type and a brief description of the function. pin no. symbol i/o function p-lcc-44 t-qfp64 stand- alone p mode power supply pins 1, 2 7, 8, 12 v ddd v ddd i5 v 5% digital supply voltage 5 14 gnda1 gnda1 i 0 v analog 7, 8 18, 19 v dda1 v dda1 i5 v 5% analog supply voltage 921 v ref v ref o v ref pin to buffer internally generated voltage with capacitor 100 nf vs gnd 13 26 v dda2 v dda2 i5 v 5% analog supply voltage 16 30 gnda2 gnda2 i 0 v analog 23 41 gndd gndd i 0 v digital mode selection pins 310tsp i single pulse test mode for activation refer to table 3 on page 27. when active, alternating 2.5 v pulses are issued in 1.5 ms intervals. tie to gnd if not used. cs i chip select (multiplexed, demultiplexed and serial modes) : low active. 18 35 auto i auto eoc mode selection between auto- and transparent mode for eoc channel processing. (automode = (1)) rst o reset output (multiplexed, demultiplexed and serial modes): low active.
psb 21911 psf 21911 pin definitions and functions semiconductor group 14 11.97 24 43 gndd i gndd must be connected to gndd in stand- alone mode. a0 i address bus pin (demultiplexed mode) smode i serial mode pin: smode = 1 selects serial mode, smode = 0 enables the multiplexed mode. 25 44 gndd i gndd must be connected to gndd in stand- alone mode. d7 i/o data bus pin (demultiplexed modes) ad7 i/o address data bus pin (multiplexed mode) not used i (serial mode) tie to gnd. 33 55 ms0 i mode selection 0 refer to table 2 on page 26. not used i (multiplexed mode) tie to gnd. a3 i address bus pin (demultiplexed modes). not used (serial mode) tie to gnd. 35 58 ms1 i mode selection 1 refer to table 2 on page 26. not used i (multiplexed mode) tie to gnd. a2 i address bus pin (demultiplexed modes). cdout o controller data out cclk determines the data rate. cdout is "high z" if no data is transmitted. pin no. symbol i/o function p-lcc-44 t-qfp64 stand- alone p mode
psb 21911 psf 21911 pin definitions and functions semiconductor group 15 11.97 36 59 ms2 i mode selection 2 refer to table 2 on page 26. not used i (multiplexed mode) tie to gnd. a1 i address bus pin (demultiplexed modes). cdin i controller data in (serial mode) cclk determines the data rate. 28 47 res res i reset low active, must be (0) at least for 10 ns. refer also to table 3 on page 27 for test modes invoked with this pin. power controller interface pins 44 5 pcd0 i/o (pu) data bus 0 of power controller interface internal pull-up. ad0 i/o address/data bus pin (multiplexed mode) d0 i/o data bus pin (demultiplexed modes) not used i (serial mode) tie to gnd. 43 4 pcd1 i/o (pu) data bus 1 of power controller interface internal pull-up. ad1 i/o address/data bus pin (multiplexed mode) d1 i/o data bus pin (demultiplexed modes) not used i (serial mode) tie to gnd. pin no. symbol i/o function p-lcc-44 t-qfp64 stand- alone p mode
psb 21911 psf 21911 pin definitions and functions semiconductor group 16 11.97 42 3 pcd2 i/o (pu) data bus 2 of power controller interface internal pull-up. ad2 i/o address/data bus pin (multiplexed mode) d2 i/o data bus pin (demultiplexed modes) not used i (serial mode) tie to gnd. 39 62 pca0 o address bus 0 of power controller interface . d5 i/o data bus pin (demultiplexed modes) ad5 i/o address data bus pin (multiplexed mode) not used i (serial mode) tie to gnd. 38 61 pca1 o address bus 1 of power controller interface d6 i/o data bus pin (demultiplexed modes) ad6 i/o address data bus pin (multiplexed mode) not used i (serial mode) tie to gnd. 41 2 pcrd o power controller bus read request low active. d3 i/o data bus pin (demultiplexed modes) ad3 i/o address/data bus pin (multiplexed mode) not used i (serial mode) tie to gnd. pin no. symbol i/o function p-lcc-44 t-qfp64 stand- alone p mode
psb 21911 psf 21911 pin definitions and functions semiconductor group 17 11.97 40 1 pcwr o power controller bus write request low active. d4 i/o data bus pin (demultiplexed modes) ad4 i/o address/data bus pin (multiplexed mode) not used i (serial mode) tie to gnd. 19 36 int i interrupt change-sensitive. after a change of level has been detected the c/i code int will be issued on iom. tie to gnd if not used. int o interrupt line (multiplexed, demultiplexed and serial modes): low active . 37 60 diss o disable power supply this pin is set to 1 after receipt of mon-0 lbbd in eoc auto-mode. mclk o microprocessor clock output (multiplexed, demultiplexed and serial modes): provided with four programmable clock rates: 7.68 mhz, 3.84 mhz, 1.92 mhz and 0.96 mhz. 21 38 ps1 ps1 i power status 1 (primary) . 1 indicates primary power supply ok. the pin level is identical to the overhead bit ps1 value. 22 39 ps2 ps2 i power status 2 (secondary) 1 indicates secondary power supply ok. the pin level is identical to the overhead bit ps2 value. pin no. symbol i/o function p-lcc-44 t-qfp64 stand- alone p mode
psb 21911 psf 21911 pin definitions and functions semiconductor group 18 11.97 miscellaneous function pins 10 22 xout xout o crystal out to connect 15.36-mhz crystal. leave open if not used. 11 23 xin xin i crystal in to connect 15.36-mhz crystal or external 15.36-mhz clock. 17 32 dod i dout open drain select open drain with dod = (1) (external pull-up resistor required) and tristate with dod = (0). see also table 4 on page 27. wr i write (siemens/intel multiplexed and demultiplexed modes): indicates a write operation, active low. r/w i read/write (motorola demultiplexed mode): indicates a read (high) or write (low) operation. not used i (serial mode) tie to gnd. 29 51 tp tp i (pd) test pin not available to user. do not connect. internal pull-down resistor. 20 37 tp1 i (pd) test pin 1 not available to user. do not connect. internal pull-down resistor. ale i address latch enable (multiplexed mode): in the siemens/ intel p interface modes a high indicates an address on the ad0..3 pins which is latched with the falling edge of ale (see also page 39). pin no. symbol i/o function p-lcc-44 t-qfp64 stand- alone p mode
psb 21911 psf 21911 pin definitions and functions semiconductor group 19 11.97 ale i address latch enable (demultiplexed mode): ale tied to gnd selects the siemens/intel type. ale tied to vdd selects the motorola type. cclk i controller data clock (serial mode): shifts data from (1) and to (0) the device. 32 54 cls cls o clock signal a 7.68mhz clock, synchronous to the u-interface, is provided on this pin. 12 24 pmod e pmode i (pd) processor interface enable setting pmode to 1 enables the processor interface . tie to gnd or do not connect to select stand-alone mode. internal pull down. 34 57 mto i (pd) monitor procedure time-out disables the internal 6 ms monitor time-out when set to (1). internal pull- down resistor. rd i read (siemens/intel multiplexed and demultiplexed modes): indicates a read operation, active low. ds i data strobe (motorola demultiplexed mode): indicates a data transfer, active low. not used i (serial mode) tie to gnd. 6, 9, 11, 15, 20, 25, 27, 31, 33, 34, 40, 48, 49, 50, 51, 63, 64 not used not used leave open for future compatibility. pin no. symbol i/o function p-lcc-44 t-qfp64 stand- alone p mode
psb 21911 psf 21911 pin definitions and functions semiconductor group 20 11.97 pu: internal pull-up resistor pd: internal pull-down resistor iom ? -2 pins 31 53 dcl dcl o data clock data clock output 512 or 1536 khz (table 2 on page 26). in p mode this pin can be programmed to deliver a bit clock (256 or 768 khz). 30 52 fsc fsc o frame synchronization clock the start of the b1-channel in time-slot 0 is marked. fsc = (1) for one dcl- period indicates a superframe marker. fsc = (1) for at least two dcl-periods marks a standard frame. 26 45 din din i data in input of iom-2 data synchronous to dcl-clock (data upstream direction). 27 46 dout dout o data out output of iom-2 data synchronous to dcl-clock. open drain or tristate depending on bit/pin dod (data downstream direction). u-interface pins 15 29 ain ain i differential u-interface input connect to hybrid. 14 28 bin bin i differential u-interface input connect to hybrid. 6 16 aout aout o differential u-interface output connect to hybrid. 4 13 bout bout o differential u-interface output connect to hybrid. pin no. symbol i/o function p-lcc-44 t-qfp64 stand- alone p mode
psb 21911 psf 21911 microprocessor bus interface (overview) semiconductor group 21 11.97 1.6 microprocessor bus interface (overview) the table below gives an overview of the different microprocessor bus modes. table 1 microprocessor bus interface pin number stand-alone mode symbol in processor mode p-lcc 44 t-qfp 64 siemens/ intel multiplexed siemens/ intel demultiplexed motorola demultiplexed serial 12 24 pmode = 0 pmode = 1 455pcd0ad0d0d0n.c. 434pcd1ad1d1d1n.c. 423pcd2ad2d2d2n.c. 41 2 pcrd ad3d3d3n.c. 40 1 pcwr ad4d4d4n.c. 39 62 pca0 ad5 d5 d5 n.c. 38 61 pca1 ad6 d6 d6 n.c. 25 44 gndd ad7 d7 d7 n.c. 19 36 int int int int int 24 43 gndd smode=0 a0 a0 smode=1 36 59 ms2 n.c. a1 a1 cdin 35 58 ms1 n.c. a2 a2 cdout 33 55 ms0 n.c. a3 a3 n.c. 20 37 tp1 ale ale=0 ale=1 cclk 34 57 mto rd rd ds n.c. 17 32 dod wr wr r/w n.c. 310tsp cs cs cs cs 37 60 diss mclk 18 35 auto rst
psb 21911 psf 21911 system integration semiconductor group 22 11.97 1.7 system integration due to the iom-2 interface the iec-q te can be combined with a variety of other devices to fit in numerous applications. this chapter only shows some typical applications of the iec-q te. 1.7.1 isdn pc adapter card an isdn adapter card which supports the u-interface may be realized using the iec-q te together with the psb 2113 3pac ( figure 5 ). the 3pac provides a d-channel and two b-channel hdlc controllers. optionally, a psb 2132 sicofi2-te can be connected to provide two pots interfaces. if an s-interface is required, the psb 2115 ipac can be used instead of the 3pac. figure 5 isdn pc adapter card
psb 21911 psf 21911 system integration semiconductor group 23 11.97 1.7.2 isdn stand-alone terminal with pots interface the iec-q te can be integrated in a microcontroller based stand-alone terminal (figure 6) that is connected to the communications interface of a pc. the psb 2132 sicofi-te enables connection of analog terminals (e.g. telephones or fax) to its dual channel pots interface. figure 6 isdn stand-alone terminal with pots interface
psb 21911 psf 21911 system integration semiconductor group 24 11.97 1.7.3 isdn feature phone an isdn feature phone with u-interface can be built using the iec-q te together with the arcofi-sp and the icc. figure 7 isdn feature phone
psb 21911 psf 21911 system integration semiconductor group 25 11.97 1.7.4 isdn-modem pc card the combination of the iec-q te and a psb 7115 isar 34 allows to build an isdn- modem pc card . figure 8 isdn-modem pc card
psb 21911 psf 21911 operating modes semiconductor group 26 11.97 2 functional description 2.1 operating modes the default configuration after power-on or external reset depends on the state of the pmode pin. the cases p mode and stand-alone mode have to be distinguished: p mode ( pmode = vdd) in p mode a microprocessor interface gives access to the iom-2 channel registers as well as configuration registers. the operating mode is selected via bits stcr:ms0-ms2 according to table 2 . the stcr register is described on page 119. test modes send single pulses, quiet mode or data through are invoked via the corresponding c/i channel command (page 75) or via bits stcr:tm1-2 ( table 3 ). stand-alone mode ( pmode = gnd) in stand-alone mode the operating mode is selected via pin strapping according to table 2 . it is possible to change the mode of a device during operation (e.g. for test purposes) if the mode change is followed by a reset. the test modes send single pulses (ssp), quiet mode (qm) and data through (dt) are invoked via the corresponding c/i channel command (page 75) or via pins res and tsp ( table 3 ). notes: 1) 1 dcl-period high-phase of fsc at superframe position 2 dcl-periods high-phase of fsc at normal position 2) cls-clock signal not available while device is in power-down table 2 modes of operation (p and stand-alone mode) mode selection output pins u synchronized mode bit/pin ms2 bit/pin ms1 bit/pin ms0 dcl out cls out super- frame- marker 1) nt 0 0 0 512 7680 2) no nt 1 0 0 512 7680 2) yes nt-auto 0 0 1 512 7680 2) no te 0 1 0 1536 7680 2) no te 1 1 0 1536 7680 2) yes reserved others
psb 21911 psf 21911 operating modes semiconductor group 27 11.97 table 3 test modes table 4 dout driver modes 1) used for quiet mode and return loss measurements 2) used for pulse mask measurements 3) used for insertion loss, power spectral density and total power measurements 1) in stand-alone mode and p mode 2) only in stand-alone mode. in p mode the output driver of pin dout is selected via bit dod in the adf2 register 3) external pull-up resistors required (typ.1 k w ) test-mode bit tm1/ pin res bit tm2/ pin tsp master-reset 1) 00 send single-pulses 2) 11 data-through 3) 01 normal 1 0 mode pin res 1) pin tsp 2) pin / bit dod pin dout output driver value dout in active time slot dout in passive time slot pin-reset 0 0 x 0 low int. pull-up 1 int. pull-up normal (tristate) 1000low high z 1high normal (open drain 3) ) 1010low floating 1floating
psb 21911 psf 21911 device architecture semiconductor group 28 11.97 2.2 device architecture in p mode the following interfaces and functional blocks are used: ? iom-2 interface see pp. 30 ? microprocessor interface pp. 39, 81, 112 ? u-transceiver pp. 40 ? clock generation pp. 111 ? reset pp. 93 ? factory test unit figure 9 iec-q te device architecture (p mode)
psb 21911 psf 21911 device architecture semiconductor group 29 11.97 in stand-alone mode the following interfaces and functional blocks are used: ? mode selection see pp. 26 ? iom-2 interface pp. 30 ? iom-2 configuration pp. 36, 38 ? u-transceiver pp. 40 ? clock generation pp. 111 ? reset pp. 93 ? power controller interface pp. 94 ? factory test unit figure 10 iec-q te device architecture (stand-alone mode)
psb 21911 psf 21911 iom?-2 interface semiconductor group 30 11.97 2.3 iom ? -2 interface the iom-2 interface is used to interconnect telecommunication ics. it provides a symmetrical full-duplex communication link, containing user data, control/programming and status channels. the structure used follows the 2b + 1d-channel structure of isdn. the isdn user data rate of 144 kbit/s (b1 + b2 + d) is transmitted in both directions over the interface. the iom-2 interface is a generalization and enhancement of the iom-1 interface. 2.3.1 iom ? -2 frame structure the iom-2 interface comprises two clock lines for synchronization and two data lines. data is carried over data upstream (du) and data downstream (dd) signals. the downstream and upstream direction are always defined with respect to the exchange. downstream refers to information flow from the exchange to the subscriber and upstream vice versa respectively. the iom-2 interface specification describes open drain data lines with external pull-up resistors. however, if operation is logically point-to- point, tristate operation is possible as well. the data is clocked by a data clock (dcl) that operates at twice the data rate. frames are delimited by an 8-khz frame synchronization clock (fsc). incoming data is sampled on every second falling edge of the dcl clock. figure 11 iom ? -2 clocks and data lines within one fsc period 32 bit or 96 bit are transmitted, corresponding to dcl frequencies of 512 khz or 1.536 mhz. two optimized iom-2 timing modes exist: C nt mode for nt1 applications C te mode for terminal and intelligent nt applications
psb 21911 psf 21911 iom?-2 interface semiconductor group 31 11.97 nt or te mode is selected via pins ms0-2 in stand-alone mode and via bits ms0-2 in p mode. both the nt and te mode utilize the same basic frame and clocking structure, but differ in the number and usage of the individual channels. figure 12 basic channel structure of iom ? -2 each frame consists of ? two 64 kbit/s channels b1 and b2 ? the monitor channel for transferring maintenance information ? two bits for the 16 kbit/s d-channel ? four command/indication (c/i) bits for controlling of layer-1 functions (u- and s- transceiver). ? two bits mr and mx for the handshake procedure in the monitor channel 2.3.1.1 te mode frame structure in te mode the iec-q te provides a data clock dcl with a frequency of 1536 khz. as a consequence the iom-2 interface provides three channels each with a nominal data rate of 256 kbit/s. ? channel 0 contains 144 kbit/s (for 2b+d) plus monitor and command/indication channels for the layer-1 device. ? channel 1 contains two 64-kbit/s intercommunication channels plus monitor and command/indication channels for other iom-2 devices. ? channel 2 is used for iom bus arbitration (access to the tic bus). only the command/ indication bits are used in channel 2. the iom-2 signals are: din, dout 768 kbit/s dcl 1536 khz output fsc 8 khz output
psb 21911 psf 21911 iom?-2 interface semiconductor group 32 11.97 figure 13 definition of the iom ? -2 frame in te mode C c/i0 in iom ? -2 channel 0: d: two bits for the 16 kbit/s d-channel c/i: the four command/indication (c/i) bits are used for control of the u- transceiver (activation/deactivation and additional control functions). mr , mx: two bits mr and mx for the handshake in the monitor channel 0 C c/i1 in iom ? -2 channel 1: c/i1 to c/i6 are used for control of a transceiver or an other device in iom-2 channel 1 (activation/deactivation and additional control functions). mr , mx: two bits mr and mx for handshake in the monitor channel 1 du / dd d d c/i4 c/i3 c/i2 c/i1 mr mx du / dd c/i6 c/i5 c/i4 c/i3 c/i2 c/i1 mr mx itd09787 dd b1 b2 mon0 c/i0 ic1 ic2 mon1 c/i1 fsc c/i1 mon1 ic2 ic1 c/i0 mon0 b2 b1 du channel 0 c/i2 c/i2 125 m s b1 b1 r iom channel iom r 1 channel r iom 2
psb 21911 psf 21911 iom?-2 interface semiconductor group 33 11.97 C c/i2 in iom ? -2 channel 2: e: d-echo bits bac-bit (bus accessed). when the tic bus is occupied the bac-bit is low. s/g-bit (stop/go), available to a connected hdlc controller to determine if it can access the d-channel (s/g = 1: stop, s/g = 0: go). a/b-bit (available/blocked), supplementary bit for d-channel control. (a/b = 1: d-channel available, a/b = 0: d-channel blocked). tba0-2: tic bus address 2.3.1.2 nt mode structure in nt mode the iec-q te provides a data clock dcl with a frequency of 512 khz. as a consequence the iom-2 interface provides only one channel with a nominal data rate of 256 kbit/s. ? channel 0 contains 144 kbit/s (for 2b+d) plus monitor and command/indication channels. the iom-2 signals are: din, dout 256 kbit/s dcl 512 khz output fsc 8 khz output figure 14 definition of the iom ? -2 frame in nt mode du 1 1 bac tba2 tba1 tba0 1 1 dd ees/ga/b1111 itd09788 b1 b2 monitor d m rx m c/i b1 b2 monitor d c/i r m x m iom channel 0 r s 125 fsc dd du
psb 21911 psf 21911 iom?-2 interface semiconductor group 34 11.97 2.3.2 iom ? -2 command / indication channels the command/indication channels carry real-time control and status information over the iom-2 interface. c/i channel 0 c/i channel 0 (c/i0) is available in both operational modes (nt and te mode). the channel consists of four bits in each direction. activation and deactivation of the u- transceiver is always controlled via the c/i0 channel. the c/i codes going to the u- transceiver are called commands, those originating from it are referred to as indications. the c/i codes of the u-transceiver are listed and explained in chapter 2.5.8 on page 74. in stand-alone mode the c/i0 channel is controlled by an external device, e.g. the icc, 3pac, ipac or isar. in p mode the c/i0 channel can either be controlled by an external device or via the microprocessor interface. for a description on how to access the c/i0 channel via the p-interface please refer to chapter 2.6.3 on page 83. c/i channel 1 c/i channel 1 (c/i1) is only available in te mode (dcl = 1.536 mhz). the channel consists of six bits in each direction. in stand-alone mode the c/i1 channel is ignored by the u-transceiver. in p mode it can be accessed via registers ciwi/u and ciri/u (page 83).
psb 21911 psf 21911 iom?-2 interface semiconductor group 35 11.97 2.3.3 iom ? -2 monitor channel the monitor channel protocol is a handshake protocol used for programming and monitoring devices in monitor channel "0" or "1". these can include the on-chip u- transceiver of the iec-q te as well as external devices connected to the iom-2 interface. the monitor channel operates on an asynchronous basis. while data transfers on the bus take place synchronized to frame sync, the flow of data is controlled by a handshake procedure. for example: data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted repeatedly once per 8-khz frame until the transfer is acknowledged via the mr bit. monitor channel 0 monitor channel 0 is available in both operational modes (nt and te mode). the u- transceiver is always controlled and monitored via monitor channel 0. the monitor channel commands and indications of the u-transceiver are listed and explained on page 51-61. in stand-alone mode the monitor channel is controlled by an external device, e.g. the icc, 3pac, ipac or isar. in p mode the monitor channel can either be controlled by an external device or via the microprocessor interface. for a description on how to access the monitor 0 channel via the p-interface please refer to chapter 2.6.4 on page 84. monitor channel 1 monitor channel 1 is only available in te mode (dcl = 1.536 mhz). the channel consists of six bits in each direction. in stand-alone mode the monitor 1 channel is ignored by the u-transceiver. in p mode it can be accessed via the microprocessor interface (page 83) to control an external device (e.g. arcofi).
psb 21911 psf 21911 iom?-2 interface semiconductor group 36 11.97 monitor procedure timeout the u-transceiver offers an automatic reset (monitor procedure timeout) for the monitor routine. this reset function transfers the monitor channel into the idle state (mr and mx set to high) by issuing eom (end of message) after a timer has elapsed. as an effect, unacknowledged monitor messages sent by the u-transceiver are taken away from the monitor channel. the u-transceiver checks for unacknowledged monitor messages every 5 ms. in case the timer expires eom will be issued. the u-transceiver does not repeat the message, hence it will be lost. in slow applications e.g. testing or evalution platforms this internal reset function may be disabled by setting C pin mto in stand-alone mode C bit adf2:mto in p mode. if monitor timeout is disabled, no restrictions regarding the time for completing a monitor transfer exists.
psb 21911 psf 21911 iom?-2 interface semiconductor group 37 11.97 2.3.4 activation/deactivation of iom ? -2 clocks the iom-2 clocks may be switched off if the u-transceiver is in state deactivated. this reduces power consumption to a minimum. in this deactivated state the clock lines are low and the data lines are high. the power-down condition within the deactivated state will only be entered if no monitor messages are pending on iom-2. for information on how to keep the iom-2 clocks active in all states please refer to the application note providing clocks in deactivated state of 09.97. the deactivation procedure is shown in figure 15 . after detecting the code di (deactivation indication) the u-transceiver responds by transmitting dc (deactivation confirmation) during subsequent frames and stops the timing signals after the fourth frame. figure 15 deactivation of the iom ? -2 clocks the iom-2 clocks are activated automatically when the din line is pulled low or a line activation is detected on the u-interface. if a psb 2186 (isac-s te) or peb 2070 (icc) is connected to the iec-q te via iom-2, the din line of the iec-q te is pulled low by itd10292 di di di di di di fsc din dout dc dc dc dc dr dr detail see fig.b din dcl dc/ ii / c i / c i / c deactivated deactivated a) b) r iom -2 interface iom -2 interface r
psb 21911 psf 21911 iom?-2 interface semiconductor group 38 11.97 setting the spu bit of the isac-s te or icc to 1. otherwise, the du line has to be pulled to low via an i/o port of the microcontroller dcl is activated such that its first rising edge occurs with the beginning of the bit following the c/i0 channel. after the clocks have been enabled this is indicated by the pu code in the c/i0 channel. 2.3.5 superframe marker the start of a new superframe on the u-interface may be indicated with a fsc high- phase lasting for one single dcl-period. a fsc high-phase of two dcl-periods is transmitted for all other iom-2 frame starts. the superframe marker is disabled if pin/bit ms2 = 0. 2.3.6 iom ? -2 output driver selection in p mode the output type of the iom dataline dout is selectable via bit adf2:dod. in stand-alone mode it is configured via pin dod. bit/pin dod set to 0 selects tristate (reset value) and dod set to 1 selects open drain outputs. in the "open drain" mode pull-up resistors (1 k w C5k w ) are required on dout. fsc and dcl always are push pull.
psb 21911 psf 21911 microprocessor interface semiconductor group 39 11.97 2.4 microprocessor interface the parallel/serial microprocessor interface can be selected to be either of the 1. siemens/intel non-multiplexed bus type with control signals cs , wr , r d 2. motorola type with control signals cs , r/w , ds 3. siemens/intel multiplexed address/data bus type with control signals cs , wr , rd , ale 4. serial mode using control signals cdin, cdout, cclk and cs . the selection is performed via pins ale/cclk and smode as follows: the occurrence of an edge on ale/cclk, either positive or negative, at any time during the operation immediately selects interface type 3 or 4. a return to one of the other interface types is possible only if a hardware reset is issued. 2.4.1 microprocessor clock output the microprocessor clock is provided in p mode on the mclk-output. four clock rates are provided by a programmable prescaler. these are 7.68 mhz, 3.84 mhz, 1.92 mhz and 0.96 mhz. switching between the clock rates is realized without spikes. the oscillator remains active all the time. the clock is synchronized to the 15.36 mhz clock at the xin pin. 2.4.2 watchdog timer the watchdog is enabled by setting the swst:wt bit to 1. the value of swst:wt after hardware reset (pin res low and pin tsp low) is "0". after the microcontroller has enabled the watchdog timer it has to write the bit patterns 10 and 01 in adf:wtc1 and adf:wtc2 within a period of 132 ms. if it fails to do so, a reset signal of 5 ms at pin rst is generated. the clock at pin mclk remains active during this reset. table 5 microprocessor interface modes ale smode siemens/intel non-mux 0 x motorola 1 x siemens/intel mux edge 0 serial edge 1
psb 21911 psf 21911 u-transceiver semiconductor group 40 11.97 2.5 u-transceiver the u-interface establishes the direct link between the exchange and the terminal side over two copper wires. transmission over the u-interface is performed at a rate of 80 kbaud. the code used is reducing two binary informations to one quaternary symbol (2b1q) resulting in a total of 160 kbit/s to be transmitted. 144 kbit/s are user data (2b + d), 16 kbit/s are used for maintenance and synchronization information. the iec-q te uses two differential outputs (aout, bout) and two differential inputs (ain, bin) for transmission and reception. these differential signals are coupled via a hybrid and a transformer to the two-wire u-interface. figure 16 shows a block diagram of the u-transceiver which can be subdivided in three main blocks: siu system interface unit rec receiver liu line interface unit the system interface unit (siu) provides the connection of the u- and the iom- interfaces. after scrambling/descrambling and rate adaptation the data channels (2b + d) are transferred to the appropriate frame. complete activation and deactivation procedures are implemented, which are controlled by activation and deactivation indications from u- or iom-interfaces. state transition of the procedures depend on the actual status of the receiver (adaptation and synchronization) and timing functions to watch fault conditions. two different modes can be selected for maintenance functions: in the auto-mode all eoc-procedure handling and executing as specified by ansi is performed. in the transparent mode all bits are transferred transparently to the iom-2 interface without any internal processing. the receiver block (rec) performs the filter algorithmic functions using digital signal processing techniques. modules for echo cancellation, pre- and post-equalization, phase adaptation and frame detection are implemented in a modular multi-processor concept. the line interface unit (liu) contains the crystal oscillator and all of the analog functions, such as the a/d-converter and the awake unit in the receive path, the pulse- shaping d/a-converter, and the line driver in the transmit path. note: due to the integrated microprocessor interface the iec-q te v5.2 has a few s more delay from iom-2 to the u-interface than the iec-q v4.4. this may be relevant in very delay sensitive appplications like radio in the loop (ritl) and wireless pbxs.
psb 21911 psf 21911 u-transceiver semiconductor group 41 11.97 figure 16 u-transceiver block diagram itb10152 iom -2 r interface fsc dcl dout din eoc control agc timing recovery awake adapter d hybrid siu rec liu a d a framing crc eq adapter ec +
psb 21911 psf 21911 u-transceiver semiconductor group 42 11.97 2.5.1 u-frame structure each basic frame consists of 18 bits for the (inverted) synchronization word; 6 overheads bits are allocated for system functions, and 216 bits transfer the userdata of 2b + d- channel (i.e. userdata of 12 iom-frames is packed into one basic u-frame). data is grouped together into u-superframes of 12 ms. the beginning of a new superframe is marked with an inverted synchronization word (isw). each superframe consists of eight basic frames (1.5 ms) which begin with a standard synchronization word (sw) and contain 222 bits of information ( table 6 ).
psb 21911 psf 21911 u-transceiver semiconductor group 43 11.97 table 6 u-frame structure C isw inverted synchronization word (quad): C 3 C 3 + 3 + 3 + 3 C 3 + 3 C 3 C 3 C sw synchronization word (quad): + 3 + 3 C 3 C 3 C 3 + 3 C 3 + 3 + 3 C crc cyclic redundancy check C eoc embedded operation channel a = address bit d/m = data / message bit i = information (data / message) C act activation bit act = (1) C> layer 2 ready for communication C dea deactivation bit dea = (0) C> lt informs nt that it will turn off C cso cold start only cso = (1) C> nt-activation with cold start only C uoa u-only activation uoa = (0) C> u-only activated C sai s-activity indicator sai = (0) C> s-interface is deactivated C febe far-end block error febe = (0) C> far-end block error occurred C ps1 power status primary source ps1 = (1) C> primary power supply ok C ps2 power status secondary source ps2 = (1) C> secondary power supply ok C ntm nt-test mode ntm = (0) C> nt busy in test mode C aib alarm indication bit aib = (0) C> interruption (according to ansi) C nib network indication bit nib = (1) C> no function (reserved for network use) framing 2b + d overhead bits (m1 C m6) quat positions 1 C 9 10 C 117 118 118 119 119 120 120 bit positions 1 C 18 19 C 234 235 236 237 238 239 240 super frame # basic frame # sync word2b + dm1m2m3 m4 m5m6 1 1 isw 2b + d eoca1 eoca2 eoca3 act/ act 11 2sw2b + deoc d/m eoci1 eoci2 dea / ps1 1 febe 3 sw 2b + d eoci3 eoci4 eoci5 1/ ps2 crc1 crc2 4 sw 2b + d eoci6 eoci7 eoci8 1/ ntm crc3 crc4 5 sw 2b + d eoca1 eoca2 eoca3 1/ cso crc5 crc6 6sw2b + deoc d/m eoci1 eoci2 1 crc7 crc8 7 sw 2b + d eoci3 eoci4 eoci5 uoa / sai crc9 crc10 8 sw 2b + d eoci6 eoci7 eoci8 aib / nib crc11 crc12 2,3 lt- to nt dir. > / < nt- to lt dir.
psb 21911 psf 21911 u-transceiver semiconductor group 44 11.97 2.5.1.1 cyclic redundancy check the cyclic redundancy check provides a possibility to verify the correct transmission of data. the checksum of a transmitted u-superframe is calculated from the bits in the d- channel, both b-channels, and the m4 bits according to the crc polynominal g (u) = u 12 + u 11 + u 3 + u 2 + u + 1 (+ modulo 2 addition) the check digits (crc bits crc1, crc2, , crc12) generated are transmitted at position m5 and m6 in the u-superframe. at the receiving side this value is compared with the value calculated from the received superframe. in case these values are not identical a crc-error will be indicated to both sides of the u-interface. it is indicated as a nebe (near-end block error) on the side where the error is detected and as a febe (far-end block error) on the remote side. the febe-bit will be placed in the next available u-superframe transmitted to the originator. far-end or near-end error indications increment the corresponding block error counters of exchange and terminal side. the iec-q te additionally issues a mon-1 message every time a nebe or febe has occurred (chapter 2.5.3, page 54). the block error counters can be read via mon-8 commands (refer to chapter 2.5.5, page 59). it is not possible to directly access the crc-checksum itself. hence the user cannot read or write the checksum values. figure 17 illustrates the crc-process. due to the scrambling algorithm described hereafter, a wrong bit decision in the receiver automatically leads to at least three bit errors. whether all of these are recorded by a bit error counter depends on whether all faulty bits are part of the monitored channels (2b+d, m4) or not.
psb 21911 psf 21911 u-transceiver semiconductor group 45 11.97 figure 17 crc-process itd10196 dd nt sfr(n) sfr(n+1) lt u g(u) crc 1... crc12 no =? yes sfr(n+1.0625) sfr(4n+1.0625) febe = "1" febe = "0" sfr(n+0.0625) nebe error counter (mon-1) nebe (mon-8) du (mon-8) (mon-1) febe febe error counter g(u) sfr(n+1.0625) sfr(n+2) sfr(n+2) febe = "0" febe = "1" dd g(u) febe error counter g(u) =? nebe error counter (2b + d), m4 du (mon-8) (mon-8) no yes (2b + d), m4 12 crc ... 1 crc 12 crc ... 1 crc crc 1... crc12 r iom -2 r iom -2 iec-q te dfe-q or iec-q
psb 21911 psf 21911 u-transceiver semiconductor group 46 11.97 2.5.1.2 block error counters the u-transceiver provides internal counters for far-end and near-end block errors. this allows a comfortable surveillance of the transmission quality at the u-interface. in addition, mon-1 messages indicate the occurrence of near-end errors, far-end errors, and the simultaneous occurrence of both errors. a block error is detected each time when the calculated checksum of the received data does not correspond to the control checksum transmitted in the following superframe. one block error thus indicates that one u-superframe has not been transmitted correctly. no conclusion with respect to the number of bit errors is therefore possible. the following two sections describe the operation of near and far-end block error counters as well as the commands available to test them. near-end and far-end block error counter a near-end block error (nebe) indicates that the error has been detected in the receive direction (i.e. nebe in the nt after an lt --> nt error). this will be indicated with a mon- 1-message nebe. each detected nebe-error increments the 8-bit nebe-counter. when reaching the maximum count, counting is stopped and the counter value reads (ff h ). the current value of the nebe counter is read with the mon-8 command rben. the response comprises two bytes: the first byte always indicates that a mon-8 message is replied to (80 h ), the second represents the counter value (00 h ) (ff h ). each read operation resets the counter to (00 h ). a far-end block error identifies errors in transmission direction (i.e. febe in the nt = nt => lt-error). febe errors are processed in the same manner as nebe errors. a far-end block error will be indicated with a mon-1 message febe. the febe counter is read and reset with the mon-8 command rbef. in case both, far-end and near-end block errors occur simultaneously, the mon-1 message fnbe will be issued. both counters are also reset in all u-transceiver states except synchronized, wait for act, transparent and error s/t.
psb 21911 psf 21911 u-transceiver semiconductor group 47 11.97 testing block error counters figure 18 illustrates how the iec-q te supports testing of the lts block error counters. transmission errors are simulated with artificially corrupted crcs. with two commands the cyclic redundancy checksum can be inverted in the downstream and in the upstream direction. a third command offers to invert single febe-bits. with eoc command ncc the lt notifies the nt of corrupted crcs. again, there are differences in the functional behavior of the nebe-counter depending on the eoc mode: auto-mode nebe-detection stopped, no mon-1 nebe-messages and nebe-counter disabled transparent mode nebe-detection enabled, mon-1-message nebe issued and nebe-counter enabled with eoc command rcc the lt requests the nt-side to send corrupted crcs. in eoc auto mode the iec-q te will react automatically with a permanently inverted upstream crc. in eoc transparent mode this reaction has to be prompted by a mon-8 ccrc command. note that mon-8 ccrc is not excecuted if it was not preceeded by the eoc command rcc. there are also differences in the functional behavior of the febe-counter depending on the eoc mode: eoc auto mode febe-detection stopped, no mon-1 febe-messages and febe-counter disabled transparent mode febe-detection enabled, mon-1-message febe issued and febe-counter en abled the eoc command rtn disables all previously sent eoc commands. in eoc transparent mode eoc command rtn must be followed by a mon-8 norm command to become effective. with the mon-8-command sfb it is possible to invert single febe-bits. because this command does not provoke permanent febe-bit inversion but sets only one febe-bit to (0) per sfb command, it is possible to predict the exact febe-counter reading.
psb 21911 psf 21911 u-transceiver semiconductor group 48 11.97 figure 18 block error counter test itd10197 eoc transparent iom r -2 (mon-0) ncc (mon-0) ack (mon-1) nebe error count nebe (mon-0) ack (mon-0) rtn (mon-0) rcc (mon-0) ack (mon-1) febe (mon-8) ccrc (mon-0) rtn (mon-0) ack error count febe eoc auto-mode stop error detect free error detect free error detect error stop detect lt u eoc acknowledge start inverse crc bits febe = "0" eoc acknowledge eoc acknowledge start inverse crc bits febe = "0" eoc eoc acknowledge end inverse crc bits : rtn eoc : rcc eoc : rtn eoc : ncc (mon-0) ack (mon-0) ncc (mon-8) ccrc (mon-8) rbef (mon-8) norm (mon-0) rtn (mon-0) ack (mon-0) ack (mon-0) rcc (mon-8) rben (mon-0) rtn error count febe nebe count error -2 r iom crc bits end inverse iec-q te iec-q te dfe-q/iec-q
psb 21911 psf 21911 u-transceiver semiconductor group 49 11.97 2.5.1.3 scrambler / descrambler the scrambling algorithm as defined by ansi t1.601 ensures that no sequences of permanent binary 0s or 1s are transmitted. the algorithms used for scrambling and descrambling are described in figure 19 . the scrambling/descrambling process is controlled fully by the iec-q te. hence, no influence can be taken by the user. please refer to page 77 for a description of loop 3. figure 19 scrambler / descrambler algorithms itd09730 x -1 ds di transmit scrambler in normal operation without loop-back 3 ds . x -18 -23 x . ds ds = di + -18 x . ds ds . x -23 + transmit scrambler for loop-back 3 x -1 x -1 x -1 x -1 ds do receive descrambler for loop-back 3 . do = ds + -18 xx -23 + (1 ) di ds x -1 x -1 x -1 x -1 x -1 -23 ds x . x ds . -5 ds = di + -5 ds x . + -23 ds x . -23 ds x . x ds -18 x -1 x -1 -1 x x -1 x -1 do = ds receive descrambler in normal operation without loop-back 3 do ds -1 x x -1 -5 -23 x (1 + + x) -1 x x ds . -5 x -1 -1 x ds x . -23
psb 21911 psf 21911 u-transceiver semiconductor group 50 11.97 2.5.1.4 embedded operations channel (eoc) eoc-data is inserted into the u-frame at the positions m1, m2 and m3 thereby permitting the transmission of two complete eoc-messages (2 12 bits) within one u-superframe. the eoc contains an address field, a data/message indicator (d/m) and an eight-bit information field. with the address field the destination of the transmitted message/data is defined. addresses are defined for the nt, 6 repeater stations and broadcasting. the data/message indicator needs to be set to (1) to indicate that the information field contains a message. if set to (0), numerical data is transferred to the nt. currently no numerical data transfer to or from the nt is required. from the 256 codes possible in the information field 64 are reserved for non-standard applications, 64 are reserved for internal network use and eight are defined by ansi/ etsi for diagnostic and loop-back functions. all remaining 120 free codes are available for future standardization. table 7 eoc-codes eoc address d/m information (hex) direction message function a1 a2 a3 d/m i1 - i8 000 x nt 111 x broadcast 0 0 1 1 1 0 x repeater stations no. 1 C no. 6 0 data 1 message 1 50 nt <---- lt lbbd close complete loop 1 51 nt <---- lt lb1 close loop b1 1 52 nt <---- lt lb2 close loop b2 1 53 nt <---- lt rcc request corrupt crc 1 54 nt <---- lt ncc notify of corrupt crc 1 ff nt <---- lt rtn return to normal 1 00 nt <---> lt hhold
psb 21911 psf 21911 u-transceiver semiconductor group 51 11.97 2.5.2 eoc-processor and mon-0 an eoc-processor on the chip is responsible for the correct insertion and extraction of eoc-data on the u-interface. the eoc-processor can be programmed to auto mode (default) or transparent mode via bit eoca in the umod register ( table 20 ). access to the eoc is only possible when a superframe is transmitted. this is the case in the u- transceiver states synchronized, wait for act, transparent, error s/t and pend. deac. u. in all other states the eoc-bits on the u-interface are clamped to high. figure 20 eoc-processor: auto mode, transparent mode the eoc is controlled and monitored via mon-0 commands and messages in the iom-2 monitor channel. the structure of a mon-0-message is shown below. the structure is identical in eoc auto and transparent mode. 1 aa nt ----> lt utc unable to comply 1 xx nt ----> lt ack acknowledge table 7 eoc-codes (contd) eoc address d/m information (hex) direction message function a1 a2 a3 d/m i1 - i8 auto mode excecute 3x u iom-2 mon-0 eoc echo eoc- processor u iom-2 mon-0 eoc eoc eoc mon-0 pin auto = 1 or bit stcr:auto = 1 transparent pin auto = 0 or bit stcr:auto = 0
psb 21911 psf 21911 u-transceiver semiconductor group 52 11.97 mon-0 structure addr: address C 0 = nt C 1 6 = repeater C 7 = broadcast d/m: data/message C 0 = data C 1 = message i1-i8: eoc code C 00 ff h = coded eoc command/indication eoc auto mode acknowledgment: all received eoc-frames are echoed back to the exchange immediately without triple-last-look. if an address other than (000 b ) or (111 b ) is received, a hold message with address 000 b is returned. however, there is an exception: the iec-q te will send a utc after three consecutive receptions of d/m = (0) or after an undefined command. latching: all detected eoc-commands are latched, i.e. they are valid as long as they are not disabled with the eoc rtn command or a deactivation. transfer to iom: with the triple-last-look criteria fulfilled the new eoc-command will be passed to iom-2 with one single mon-0-message, independently of the address used and the status of the d/m indicator. mon-0-commands from iom will be ignored. execution: the eoc-commands listed in table 8 will be executed automatically by the psb 21911 if they were addressed correctly (000 b or 111 b ) and the d/m bit was set to message (1). the execution of a command is performed only after the triple-last-look criterion is met. 1. byte 2. byte 0 0 0 0 a a a | x i1 i2 i3 i4 i5 i6 i7 i8 mon-0 addr. | d/m eoc code
psb 21911 psf 21911 u-transceiver semiconductor group 53 11.97 eoc transparent mode in transparent mode no acknowledgment, no triple-last-look and no execution of the received commands is performed. the received eoc-frame is transmitted directly downstream via a mon-0-message. thus, a mon-0-message is issued on iom every 6 ms. acknowledgment and execution of the received command have to be initiated by the microcontroller. the microcontroller can execute all defined test functions (close/ open loops, send corrupted crcs) in the nt using mon-8-commands. in the upstream direction the last incoming eoc-code from the iom-2-monitor channel is transmitted to the lt. table 8 executed eoc commands in auto mode eoc-code i1 - i8 (hex) direction function du 50 lbbd close complete loop-back (b1, b2, d). the u-transceiver does not close the complete loop-back immediately after receipt of this code. instead it issues the c/i-command ail (in transparent state) or arl in the states error s/t and synchronized. this allows the downstream device to close the loop-back if desired (e.g. s-transceiver or microcontroller). 51 lb1 closes b1 loop-back in nt. all b1-channel data will be looped back within the u-transceiver. 52 lb2 closes b2 loop-back in nt. all b2-channel data will be looped back within the u-transceiver. 53 rcc request corrupt crc. upon receipt the iec-q te transmits corrupted (= inverted) crcs upstream. this allows to test the near end block error counter on the lt- side. the far end block error counter at the nt-side is disabled and nt-error indications (mon-1) are suppressed. 54 ncc notify of corrupt crc. upon receipt of ncc the near end block error counter is disabled and error indications are suppressed. this prevents wrong error counts while corrupted crcs are sent. ff rtn return to normal. with this command all previously sent eoc-commands will be released. the eoc-processor is reset to its initial state (ff h ).
psb 21911 psf 21911 u-transceiver semiconductor group 54 11.97 2.5.3 maintenance (mon-1) this category comprises commands and messages relating to maintenance bits of the u-interface and the self-test according to ansi t1.601. the commands and messages may be mapped to the s/q channel of the s/t-interface via the microprocessor. this provides a method to exchange u-interface related information between a terminal on the s-bus and the nt. thus, the terminal can be informed about transmission errors that occurred on the u-interface (nebe, febe, fnbe) or request the nt to perform a self- test (st). mon-1 messages are two bytes long. the first nibble of the second byte contains s/q- indications, the second nibble contains maintenance bit related commands. the operation of mon-1-messages is identical in auto- and transparent mode. the following tables give an overview of indications available in the mon-1 category. mon-1 structure s/q: s/q-channel C 00 ff h = coded s/q-command indication m: maintenance bits C 00 ff h = set/reset maintenance bits the following indications and maintenance bits are defined in mon-1-messages. 1. byte 2. byte 0 0 0 1 0 0 0 0 s s s s m m m m mon-1 s/q-code m-bits table 9 mon-1 s/q-channel commands and indications s/q direction function ssss (bin) d u s/q-channel 0 0 0 1 st self-test request . this command is issued by the terminal to inquire whether layer 1 is present. no test is performed within the u-transceiver. upon reception the u-transceiver replies with mon-1 stp. 0 0 1 0 stp self-test pass . indicates to the terminal that the u- transceiver has received the command st correctly. 0 1 0 0 febe far-end block error . via the febe bit set to (0) on the u-interface it is indicated to the nt that transmission errors occurred in the direction nt C> lt or nt C> lt- rp.
psb 21911 psf 21911 u-transceiver semiconductor group 55 11.97 1 0 0 0 nebe near-end block error . transmission errors occurred in the direction lt C> nt. 1 1 0 0 fnbe far- and near-end block error . transmission errors were observed in lt C> nt direction. 1 1 1 1 norm normal . return to normal (idle) state. this command initiates no u-transceiver action. table 10 mon-1 m-bit commands m-bit direction function mmmm (bin) d u maintenance bits 1 x x 0 ntm nt-test mode . after reception of this command the ntm-bit of the u-interface is set active (= 0) in order to inform the exchange that the nt is involved in testing and not available for transparent transmission. this message needs to be sent out by the downstream device if the terminal requests tests which prevent transparent transmission (e.g. loops b1, b2, d). 1 1 1 1 norm normal sets back the ntm-bit to 1. no other action taken. table 9 mon-1 s/q-channel commands and indications (contd) s/q direction function ssss (bin) d u s/q-channel
psb 21911 psf 21911 u-transceiver semiconductor group 56 11.97 2.5.4 overhead bits (mon-2) mon-2-indications are used to transfer all overhead bits (m4, m5, m6) except those representing eoc- and crc-bits. starting with the act-bit, the order is identical to the position of the bits at the u-interface. table 11 mon-2 structure d0 11: overhead bits these bit positions in the mon-2-message correspond to the following overhead bits: 1. byte 2. byte 0 0 1 0 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 mon-2 overhead bits overhead bits table 12 control of overhead bits position upstream (write) downstream (read) mon-2/u bit control bit control d11/m41 act u-transc. act network d10/m51 1 mon-2 1 network d9/m61 1 mon-2 1 network d8/m42 ps1 pin ps1 dea network d7/m52 1 mon-2 1 network d6/m62 febe u-transc./ mon-8 febe network d5/m43 ps2 pin ps2 1 network d4/m44 ntm mon-1 1 network d3/m45 cso u-transc. 1 network d2/m46 1 mon-2 1 network d1/m47 sai u-transc./ mon-2 uoa network d0/m48 1 mon-2 1 network
psb 21911 psf 21911 u-transceiver semiconductor group 57 11.97 control via network C all downstream bits. automatic control via u-transceiver C act (activation bit) = (1) C> layer 2 ready for communication C sai (s activity indicator) = (0) C> s-interface is deactivated; can be controlled via mon-2 after mon-8 pace. C febe (far-end block error) = (0) C> far-end block error occurred can additionally be controlled via mon-8-sfb. C cso (cold start only). = (0) C> u-transceiver is warm start capable; control via pins C ps1 (power prim. source) = (1) C> ps1 = (1) C> prim. supply ok C ps2 (power sec. source) = (1) C> ps2 = (1) C> sec. supply ok control via mon-2 C only the undefined bits marked with binary 1 C sai (s activity indicator) = (0) C> s-interface is deactivated; can be controlled via mon-2 after mon-8 pace. control via other mon-commands C ntm (nt-test mode) = (0) C> nt busy in test mode (mon-1) C febe (far-end block error);mon-8 message sfb sets a single febe bit to 0 for details about the meaning of the overhead bits please refer to etsi etr 080 and ansi t1.601. overhead bits upstream transmission C the upstream overhead bits are controlled by means of the u-transceiver due to its state, pins, mon-2 commands and other mon commands. C only the undefined bits market with binary 1 may be controlled directly by a mon-2- message. C all overhead bits are set to binary 1 when leaving a power-down state. overhead bits downstream reception C in the receive direction, the overhead bits of the last two u-interface superframes are compared and a mon-2-message defining all 12 bits is issued if a difference between both was found on at least one single bit other than the febe bit. therefore, a mon- 2-message is sent not more often than once per superframe (12 ms interval).
psb 21911 psf 21911 u-transceiver semiconductor group 58 11.97 C in order to notify the controller of the initial system status, one mon-2-message is issued immediately after reaching the synchronized state in ntmode. C the u-transceiver will not issue mon-2-messages while crc-violations are detected. because the crc-checksum is transmitted one superframe later, a maximum of one corrupted mon-2-indication can be issued. in this case a mon-2-message indicating the correct system status will be issued after the transmitted crc-checksum is again identical to the calculated checksum.
psb 21911 psf 21911 u-transceiver semiconductor group 59 11.97 2.5.5 local functions (mon-8) local functions are controlled via mon-8-commands. the following tables give an overview of structure and features of commands belonging to this category. format of mon-8-messages r: register address C 0 = local function register C 1 = internal register d07 local command C 00 ff h = local function code C 00 ff h = internal register address the following local commands are defined. if a response is expected, it will comprise 4 bytes (2 messages a 2 bytes) if the value of an internal coefficient is returned, and 2 bytes in all other cases. in a two-byte response the first byte will indicate that a mon-8 answer is transmitted, the second byte contains the requested information. this procedure is repeated for a four- byte transfer (mon-8, info 1, mon-8, info 2). 1. byte 2. byte 1 0 0 0 r | 0 0 0 d7 d6 d5 d4 d3 d2 d1 d0 mon-8 register | addr. local command (message/data) table 13 mon-8 local function commands r code direction function d7-d0 (bin) d u local commands 0 1011 1110 pace partial activation control external . with the pace-command issued, the u-transceiver will ignore the actual status of the received uoa-bit and behave as if the uoa-bit was set to (1). after issuing pace the uoa/sai-bits can be controlled by mon-2-commands. 0 1011 1111 paca partial activation control automatic . paca enables the device to interpret the uoa-bit and control the sai-bit automatically. partial activation and deactivation is therefore possible. the u-transceiver is automatically reset into this mode in the states test, receive reset and tear down.
psb 21911 psf 21911 u-transceiver semiconductor group 60 11.97 0 1111 0000 ccrc corrupt crc . this command is only recognized if the device is set to eoc transparent mode. the microcontroller should issue the command in case the mon-0- command rcc was received before. ccrc then causes corrupt crcs to be transmitted upstream. 0 1111 0100 lb1 loop-back b1 . the command is only recognized in eoc transparent mode. the microcontroller should issue the command in case the mon-0-command lb1 was received before. lb1 loops back the b1 channel. the loop is closed near the iom-2 interface. 0 1111 0010 lb2 loop-back b2 . the command is only recognized in eoc transparent mode. the microcontroller should issue the command in case the mon-0-command lb2 was received before. lb2 loops back the b2 channel. the loop is closed near the iom-2 interface. 0 1111 0001 lbbd loop-back b1 + b2 + d . the command is used in the eoc transparent and eoc auto-mode. lbbd loops back both b-channels and the d- channel. the loops are closed near the iom-2 interface. in transparent mode the loop is closed unconditionally. in auto-mode the loop is closed only if lbbd was received in the eoc-channel before. 0 1111 1111 norm return to normal . the norm-command resets the device into its default mode, i.e. loops are resolved and corrupted crcs are stopped. it is only used in transparent mode. 0 1111 1011 rben read near-end block error counter . the value of the near-end block error counter is returned and the counter is reset to zero. the maximum value is ff h . table 13 mon-8 local function commands (contd) r code direction function d7-d0 (bin) d u local commands
psb 21911 psf 21911 u-transceiver semiconductor group 61 11.97 notes: b b internal coefficient value c c internal coefficient address r r result from block error counter 0 1111 1010 rbef read far-end block error counter . the value of the far-end block error counter is returned and the counter is reset to zero. the maximum value is ff h . 0 r r r r r r r r abec answer block error counter . the value of the requested block error counter is returned (8 bit). 0 0000 0000 rid read identification . request for device identification. 0 r r r r r r r r aid answer identification . reply to an rid is 03 h . 0 1111 1001 sfb set febe bit to 0 1 cccc cccc rcoef read coeffiecient 1 1 bbbb bbbb bbbb bbbb dcoef data coefficients , 2 bytes. data bits d0 d 7, 1. byte data bits d8 d15, 2. byte table 13 mon-8 local function commands (contd) r code direction function d7-d0 (bin) d u local commands
psb 21911 psf 21911 u-transceiver semiconductor group 62 11.97 2.5.6 state machine notation rules the state machine includes all information necessary for the user to understand and predict the activation/deactivation status of the u-transceiver. the information contained in a state bubble is: state name, u-signal transmitted, single bits (overhead bits) transmitted, c/i- indication transmitted on the c/i-channel, transition criteria and timers . figure 21 state diagram notation u-transceiver the following example explains the use of the state diagram by an extract of the nt- state diagram. the state explained is the ec-training state. example: the state may be entered by either of two methods: Cfrom state alerting after time t11 has expired. Cfrom state ec-training 1 after the c/i command di has been received. the following informantion is transmitted: Csn1 is sent on the u-interface. Cno overhead bits are sent Cc/i message dc is issued on the iom-2 interface. the state is be left at occurrence of one of the following events: Cleave for state eq-training after lsec has been detected. Cleave for state eq-training after timer t12 has expired. itd04257 state name single bit transmitted to u-interface signal transmitted to u-interface (general) indication transmitted on c/i-channel (dd) in out
psb 21911 psf 21911 u-transceiver semiconductor group 63 11.97 combinations of transition criteria are possible. logical and is indicated by & (tn & dc), logical or is written or and for a negation / is used. the start of a timer is indicated with txs (x being equivalent to the timer number). timers are always started when entering the new state. the action resulting after a timer has expired is indicated by the path labelled txe. 2.5.7 state machine this chapter describes the activation and deactivation behavior of the iec-q te. it applies for both nt and te mode. 2.5.7.1 cold and warm starts two types of start-up procedures are supported by the u-transceiver: cold starts and warm starts. cold starts are performed after a reset and require all echo and equalizer coefficients to be recalculated. this procedure typically is completed after 1-7 seconds depending on the line characteristics. cold starts are recommended for activations where the line characteristics have changed considerably since the last deactivation. a warm start procedure uses the coefficient set saved during the last deactivation. it is therefore completed much faster (maximum 300 ms). warm starts are however restricted to activations where the line characteristics do not change significantly between two activations. regarding the path in the transition diagram, cold starts have in particular that the u- transceiver has entered the state test (e.g. due to a reset) prior to an activation. the activation procedure itself is then identical in both cases. therefore, the following sections apply to both warm and cold starts.
psb 21911 psf 21911 u-transceiver semiconductor group 64 11.97 2.5.7.2 state diagram figure 22 state transition diagram itd09705 any state pin-dt or dt any state pin-ssp or pin-res or ssp or res dc deactivated . 0 sn sn0 . iom pu dc alerting . tn sn1 . ec-training dc sn0 . eq-training dc sn2 . wait for sf dc dc synchronized 1 sn3/sn3t ar/arl ar/arl wait for act ai/ail transparent sn3t ar/arl error s/t sn0 . pending timing dc ar analog loop back dc wait for sf al 3 sn dc ec-training al . 1 sn sn0/sp . test dr dr ec-training 1 . 1 sn tn . alerting dr dr pend. deact. s/t 3 sn sn0 . pend. receive res. ei1 pend. deact. u dc dr receive reset . 0 sn ar or tl tim or din = 0 t14 s t14 e tl t14 s t11s t1s, t12s t11e pu lsec or t12e bbd0 & fd lsue or t1e t1e lof bbd0 & sfd act = 0 uoa = 1 act = 0 synchronized 2 uoa = 0 lsue dea = 0 dea = 0 lsue lof lof act = 1 ei1 lof act = 1 sn3t act = 0 ei 1 uoa = 0 dea = 0 lsue lsue dea = 0 uoa = 0 uoa = 0 dea = 0 lsue act = 1 act = 0 ai act = 0 lof act = 1 & ai di di t11e t12s (lsec or t12e) & di 1 lof di lsue dea = 0 act = 1/0 lsu act = 1 sn3t dea = 1 uoa = 1 ? no yes & t13e) lsu or (/lof t13s t7s tl t7s & di t7e act = 0 act = 0 sn3t arl bbd1 & sfd t14 s di awaked ar or tl di t1s, t11s t11s t1s, lsec or t12e t12s sn3/sn3t sn3/sn3t r
psb 21911 psf 21911 u-transceiver semiconductor group 65 11.97 2.5.7.3 inputs to the u-transceiver c/i-commands ai activation indication the s-transceiver issues this indication to announce that the s-receiver is synchronized. the u-transceiver informs the lt side by setting the act bit to 1. ar activation request info1 has been received by the s-transceiver or the intelligent nt wants to activate the u-interface. the u-transceiver is requested to start the activation process by sending the wake-up signal tn. arl activation request local loop-back the u-transceiver is requested to operate an analog loop-back (close to the u- interface) and to begin the start-up sequence by sending sn1 (without starting timer t1). this command may be issued only after the u-transceiver has been reset by making use of the c/i-channel code res or a hardware reset. this assures that the ec- and eq-coefficient updating algorithms converge correctly. the arl-command has to be issued continuously as long as the loop-back is required. di deactivation indication this indication is used during a deactivation procedure to inform the u- transceiver that timing signals are needed no longer and that the u-transceiver may enter the deactivated (power-down) state. the di-indication has to be issued until the u-transceiver has answered with the dc-code. din = 0 binary 0 polarity on din this asynchronous signal requests the u-transceiver to provide iom clocks. hereafter, binary 0s in the c/i-channel (code tim 0000 or any other code different from di 1111) keep the iom-2 interface active. dt data through this unconditional command is used for test purposes only and forces the u- transceiver into a state equivalent to the transparent state. the far-end transceiver is assumed to be in the same condition. ei1 error indication 1 the s-transceiver indicates an error condition on its receive side (loss of frame alignment or loss of incoming signal). the u-transceiver informs the lt-side by setting the act-bit to 0 thus indicating that transparency has been lost. res reset unconditional command which resets the whole chip; especially the ec- and eq-coefficients are set to zero.
psb 21911 psf 21911 u-transceiver semiconductor group 66 11.97 ssp send single pulses unconditional command which requests the transmission of single pulses on the u-interface. the pulses are issued at 1.5 ms intervals and have a duration of 12.5 m s. the chip is in the test state, the receiver will not be reset. tim timing in the nt-mode the u-transceiver is requested to continue providing timing signals and not to leave the power-up state. pins pin-res pin-reset corresponds to a low-level at pin res or a power-on reset. the function of this pin is the same as of the c/i-code res. c/i-message dr will be issued. the duration of the reset pulse must be longer than 10 ns. pin-ssp pin-send single pulses corresponds to a high-level at pin tsp in stand-alone mode. the function of this pin is the same as of the c/i-code ssp. c/i-message dr will be issued. the high-level must be applied continuously for single pulses. pin-dt pin-data through this function is activated when both pins res and tsp are active in stand- alone mode (res = 0 and tsp = 1). the function of this pin is the same as of the c/i-code dt. c/i-message dr will be issued. u-interface events the signals slx and tl received on the u-interface are defined in table 22 on page 100 act act-bit received from lt-side. C act = 1 requests the u-transceiver to transmit transparently in both directions. as transparency in receive direction (u-interface to iom) is already performed when the receiver is synchronized, the receipt of act = 1 establishes transparency in transmit direction (iom to u- interface), too. in the case of loop-backs, however, transparency in both directions of transmission is established when the receiver is synchronized. C act = 0 indicates that the lt-side has lost transparency.
psb 21911 psf 21911 u-transceiver semiconductor group 67 11.97 dea dea-bit received from the lt-side C dea = 0 informs the u-transceiver that a deactivation procedure has been started by the lt-side. C dea = 1 reflects the case when dea = 0 was detected by faults due to e.g. transmission errors and allows the u-transceiver to recover from this situation (see state pend. deact. u). uoa uoa-bit received from network side C uoa = 0 informs the u-transceiver that only the u-interface is to be activated. the s/t-interface must remain deactivated. C uoa = 1 enables the s/t-interface to activate. lof loss of framing on the u-interface this condition is fulfilled if framing is lost for 576 ms. 576 ms are the upper limit. if the correlation between synchronization word and the input signal is not optimal, lof may be issued earlier. lsec loss of signal level behind the echo canceler internal signal which indicates that the echo canceler has converged. lsu loss of signal level on the u-interface this signal indicates that a loss of signal level for a duration of 3 ms has been detected on the u-interface. this short response time is relevant in all cases where the nt waits for a response (no signal level) from the lt-side, i.e. after a deactivation has been announced (receipt of dea = 0), after the nt has lost framing, and after timer t1 has elapsed. lsue loss of signal level on the u-interface after a loss of signal has been noticed, a 588 ms timer is started. when it has elapsed, the lsue-criterion is fulfilled. this long response time (see also lsu) is valid in all cases where the nt is not prepared to lose signal level i.e. the lt has stopped transmission because of loss of framing, an unsuccessful activation, or the transmission line is interrupted. note that 588 ms represent a minimum value; the actual loss of signal might have occurred earlier, e.g. when a long loop is cut at the nt-side and the echo coefficients need to be readjusted to the new parameters. only after the adjusted coefficients cancel the echo completely, the loss of signal is detected and the timer can be started (if the long loop is cut at the remote end, the coefficients are still correct and loss of signal will be detected immediately). sfd superframe (isw) detected on u-interface fd frame (sw) detected on u-interface
psb 21911 psf 21911 u-transceiver semiconductor group 68 11.97 tl wake-up signal received from the lt the u-transceiver is requested to start an activation procedure. the tl- criterion is fulfilled when 12 consecutive periods of the 10-khz wake-up tone were detected. when in the pending timing state and automatic activation after reset is selected (nt-auto mode), a recognition of tl is assumed every time the pending timing state has been entered from the test state (caused by c/i code di). this behavior allows the u-transceiver to initiate one single activation attempt after having been reseted. bbd0/1 binary 0s or 1s detected in the b- and d-channels this internal signal indicates that for 6-12 ms, a continuous stream of binary 0s or 1s has been detected. it is used as a criterion that the receiver has acquired frame synchronization and both its ec- and eq-coefficients have converged. bbd0 corresponds to the signal sl2 in the case of normal activation and bbd1 corresponds to the internally received signal sn3 in case of an analog loop back in the nt-mode. timers the start of timers is indicated by txs, the expiry by txe. the following table 14 shows which timers are used by the u-transceiver: table 14 timers timer duration (ms) function state t1 15000 supervisor for start-up t7 40 hold time receive reset t11 9 tn-transmission alerting t12 5500 supervisor ec-converge ec-training t13 15000 frame synchronization pend. receive reset t14 0.5 hold time pend. timing
psb 21911 psf 21911 u-transceiver semiconductor group 69 11.97 2.5.7.4 outputs of the u-transceiver signals and indications are issued on iom-2 (c/i-indications) and on the u-interface (predefined u-signals). c/i indications ai activation indication the u-transceiver has established transparency of transmission in the direction iom to u-interface. in an nt1, the s-transceiver is requested to send info4 and to achieve transparency of transmission in the direction iom to s/ t-interface. ail activation indication loop-back the u-transceiver has detected act = 1 while loop-back 2 is still established. in an nt1, the s-transceiver is requested to send info4 (if a transparent loop- back 2 is to be implemented) and to keep loop-back 2 active. ar activation request the u-receiver has synchronized on the incoming signal. in an nt1, the s- transceiver is requested to start the activation procedure on the s/t-interface by sending info2. arl activation request loop-back the u-transceiver has detected a loop-back 2 command in the eoc-channel and has established transparency of transmission in the direction iom to u- interface. in an nt1, the s-transceiver is requested to send info2 (if a transparent loop-back 2 is to be implemented) and to operate loop-back 2. dc deactivation confirmation idle code on the iom-2 interface. the u-transceiver stays in the power-down mode unless an activation procedure has been started from the lt-side. the u-interface may be activated but the s/t-interface has to remain deactivated. dr deactivation request the u-transceiver has detected a deactivation request command from the lt- side for a complete deactivation or a s/t only deactivation. in an nt1, the s- transceiver is requested to start the deactivation procedure on the s/t- interface by sending info0. ei1 error indication 1 the u-transceiver has entered a failure condition caused by loss of framing on the u-interface or expiry of timer t1.
psb 21911 psf 21911 u-transceiver semiconductor group 70 11.97 int interrupt (stand-alone mode only) a level change on input pin int triggers the transmission of this c/i code in four successive iom-2 frames. please refer to page 96 for details. pu power up the u-transceiver provides iom-2 clocks. signals on u-interface the signals snx, tn and sp transmitted on the u-interface are defined in table 22 on page 100 . the polarity of the transmitted act-bit is as follows: a = 0/1 corresponds to act-bit set to binary 0/1 the polarity of the issued sai-bit depends on the received c/i-channel code: di and tim leads to sai = 0, any other c/i-code sets the sai-bit to 1 indicating any activity on the s/t-interface. 2.5.7.5 states the following states are used: alerting the wake-up signal tn is transmitted for a period of t11 either in response to a received wake-up signal tl or to start an activation procedure on the lt-side. alerting 1 alerting 1 state is entered when a wake-up tone was received in the receive reset state and the deactivation procedure on the nt-side was not yet finished. the transmission of wake-up tone tn is started. analog loop-back upon detection of binary 1s for a period of 6C12 ms and of the superframe indication, the analog loop-back state is entered and transparency is achieved in both directions of transmission. this state can be left by making use of any unconditional command. only the c/i-channel code res should be used, however. this assures that the ec- and eq-coefficients are set to zero and that for a subsequent normal activation procedure the receiver updating algorithms converge correctly. deactivated the deactivated state is a power-down state. if there are no pending monitor channel messages from the u-transceiver, i.e. all monitor channel messages have been
psb 21911 psf 21911 u-transceiver semiconductor group 71 11.97 acknowledged, the iom-clocks are turned off. no signal is sent on the u-interface. the u-transceiver waits for a wake-up signal tl from the lt-side to start an activation procedure. to enter state iom awake a wake-up signal (din = 0) is required if the iom- clocks are disabled. the wake-up signal is provided via the iom-2 interface (pin din = 0). if the iom-clocks were active in state deactivated c/i-code tim is sufficient for a transition to state iom awake. ec training the signal sn1 is transmitted on the u-interface to allow the nt-receiver to update the ec-coefficients. the automatic gain control (agc), the timing recovery and the eq updating algorithm are disabled. the ec-training state is left when the ec has converged (lsec) or when timer t12 has elapsed. ec-training 1 the ec-training 1 state is entered if transmission of signal sn1 has to be started and the deactivation procedure on the nt-side is not yet finished. ec-training al this state is entered in the case of an analog loop-back. the signal sn1 is transmitted on the u-interface to allow the nt-receiver to update the ec-coefficients. the automatic gain control (agc), the timing recovery and the eq updating algorithm are disabled. the ec-training state is left when the ec has converged (lsec) or when timer t12 has elapsed. eq-training the receiver waits for signal sl1 or sl2 to be able to update the agc, to recover the timing phase, to detect the synch-word (sw), and to update the eq-coefficients. the eq-training state is left upon detection of binary 0s in the b- and d-channels for a period of 6C12 ms corresponding to the detection of sl2. error s/t loss of framing or loss of incoming signal has been detected on the s/t-interface (ei1). the lt-side is informed by setting the act-bit to 0 (loss of transparency on the nt- side). the following codes are issued on the c/i-channel: C normal activation or single-channel loop-back: ar C loop-back 2: arl iom ? -2 awaked timing signals are delivered on the iom-2 interface. the u-transceiver enters the deactivated state again upon detection of the c/i-channel code di (idle code).
psb 21911 psf 21911 u-transceiver semiconductor group 72 11.97 pending deactivation of s/t the u-transceiver has received the uoa-bit at zero after a complete activation of the s/ t-interface. the u-transceiver deactivates the s/t-interface by issuing dr in the c/i- channel. the value of the act-bit depends on its value in the previous state. pending deactivation of u-interface the u-transceiver waits for the receive signal level to be turned off (lsu) to enter the receiver reset state and start the deactivation procedure. pending receive reset the pending receive reset state is entered upon detection of loss of framing on the u-interface or expiry of timer t1. this failure condition is signalled to the lt-side by turning off the transmit level (sn0). the u-transceiver then waits for a response (no signal level lsu) from the lt-side to enter the receive reset state. pending timing the pending timing state assures that the c/i-channel code dc is issued four times before the timing signals on the iom-2 interface are turned off. in case the nt-auto mode (pin aua=1) is selected the recognition of the lt wake-up tone tl is assumed everytime the pending timing state has been entered from the test state. this function guarantees that the nt (in nt-auto mode) starts one single activation attempt after having been resetted. after the assumed tl recognition in this state the activation will proceed normally. receive reset the receive reset state is entered upon detection of a deactivation request from the lt-side, after a failure condition on the u-interface (loss of signal level lsue), or following the pending reset state upon expiry of timer t1 or loss of framing. no signal is transmitted on the u-interface, especially no wake-up signal tn, and the s-transceiver or microcontroller is requested to start the deactivation procedure on the nt-side (dr). timer t7 assures that no activation procedure is started from the nt-side for a minimum period of t7. this gives the lt a chance to activate the nt. the state is left only after completion of the deactivation procedure on the nt-side (receipt of the c/i-channel code di), unless a wake-up tone is received from the lt-side.
psb 21911 psf 21911 u-transceiver semiconductor group 73 11.97 synchronized 1 when reaching this state the u-transceiver informs the lt-side by sending the superframe indication (inverted synch.-word). the loop-back commands decoded by the eoc-processor control the output of the transmit signals: C normal act and uoa = 0: sn3 C any loop-back and uoa = 0 (no loop-back): sn3t the value of the issued sai-bit depends on the received c/i-channel code: di and tim lead to sai = 0, any other c/i-code sets the sai-bit to 1 indicating activity on the s/t- interface. the u-transceiver waits for the receipt of uoa = 1 to enter the synchronized 2 state. synchronized 2 in this state the u-transceiver has received uoa = 1. this is a request to activate the s/t-reference point. the loop-back commands detected by the eoc-processor control the output of indications and transmit signals: C normal activation and uoa = (1): sn3 and ar C single channel loop-back and uoa = (1): sn3t and ar C loop-back 2 (lbbd): sn3t and arl the value of the issued sai-bit depends on the received c/i-channel code: di and tim lead to sai = 0, any other c/i-code sets the sai-bit to 1 indicating activity on the s/t- interface. the u-transceiver waits for the receipt of the c/i-channel code ai to enter the wait for act state. test the test mode is entered when the unconditional commands res, ssp, pin-res or pin-ssp are used. it is left when normal u-transceiver operation is selected via pins res and tsp and the c/i-channel codes di or arl are received. the following signals are transmitted on the u-interface: C no signal level (sn0) when the c/i-channel code res is applied or a hardware reset is activated. C single pulses (sp) when the c/i-channel code ssp is applied or pin tsp =1. transparent this state is entered upon the detection of act = 1 received from the lt-side and corresponds to the fully active state. in the case of a normal activation in both directions of transmission the the following codes are output: C normal activation or single-channel loop-back: ai C loop-back 2: ail
psb 21911 psf 21911 u-transceiver semiconductor group 74 11.97 wait for act upon the receipt of ai, the act-bit is set to 1 and the nt waits for a response (act = 1) from the lt-side. the output of indications and transmit signals is as defined for the synchronized state. wait for sf upon detection of sl2, the signal sn2 is sent on the u-interface and the receiver waits for detection of the superframe indication. timer t1 is then stopped and the synchronized state is entered. wait for sf al this state is entered in the case of an analog loop-back and allows the receiver to update the agc, to recover the timing phase, and to update the eq-coefficients. signal sn3 is sent instead of signal sn2 in the wait-for-sf state. 2.5.8 c/i codes both commands and indications depend on the data direction. table 15 presents all defined c/i codes. a new command or indication will be recognized as valid after it has been detected in two successive iom frames (double last-look criterion). indications are strictly state orientated. refer to the state diagrams in the previous sections for commands and indications applicable in various states.
psb 21911 psf 21911 u-transceiver semiconductor group 75 11.97 table 15 u-transceiver c/i codes code nt-mode in out 0000 tim dr 0001 res C 0010 C C 0011 C C 0100 ei1 ei1 0101 ssp C 0110 dt int 0111 C pu 1000 ar ar 1001 C C 1010 arl arl 1011 C C 1100 ai ai 1101 C C 1110 C ail 1111 di dc ai activation indication ei1 error indication 1 ar activation request int interrupt arl activation request local loop pu power-up dc deactivation confirmation res reset di deactivation indication ssp send-single-pulses test mode dr deactivation request tim timing request dt data-through test mode
psb 21911 psf 21911 u-transceiver semiconductor group 76 11.97 2.5.9 layer 1 loop-backs test loop-backs are specified by the national ptts in order to facilitate the location of defect systems. four different loop-backs are defined. the position of each loop-back is illustrated in figure 23 . figure 23 test loop-backs supported by the iec-q te loop-backs #1, #1a and #2 are controlled by the exchange. loop-backs #3 is controlled by the terminal. all loop-back types are transparent. this means all bits that are looped back will also be passed onwards in the normal manner. 2.5.9.1 loop-back (no. 2) normally loop-back #2 is controlled from the exchange via the eoc commands lbbd, lb1 and lb2. in eoc auto mode the eoc commands are recognized and executed automatically (see page 51). the single channel loop-backs (lb1, lb2) are closed in the u-transceiver itself whereas the complete loop-back (lbbd) is closed in a connected s- transceiver. all loop-back functions are latched. this allows channel b1 and channel b2 to be looped back simultaneously. all loop-backs are opened when the eoc command rtn is sent by the lt. itd10198 loop 2 2 loop s-bus iom r sbcx iec-q te nt icc r iom loop 2 3 loop icc pbx or te iec-q iec-q r iom 1a loop uu repeater (optional) loop 1 iec-q iom r exchange iec-q te iec-q te
psb 21911 psf 21911 u-transceiver semiconductor group 77 11.97 complete loop-back the complete loop-back comprises both b-channels and the d-channel. it may be closed either in the u-transceiver itself , in the s-transceiver or in an external device. when receiving the eoc-command lbbd in eoc auto mode, the u-transceiver does not close the loop-back immediately. because the intention of this loop-back is to test the complete nt, the u-transceiver passes the complete loop-back request on to the iom-2 interface. this is achieved by issuing the c/i-code ail in the transparent state or c/i = arl in states different than transparent. in applications that include a microcontroller, the software decides where to close the loop, whereas in an nt1 the loop is closed automatically in the s-transceiver (e.g. sbcx). single-channel loop-back (b1/b2) single-channel loop-backs are always performed directly in the u-transceiver if eoc auto mode is selected. no difference between the b1-channel and the b2-channel loop- back control procedure exists. they are therefore discussed together. the b1-channel is closed with the eoc-command lb1. lb2 causes the channel b2 to loop-back. because these functions are latched, both channels may be looped back simultaneously by sending first the command to close one channel followed by the command for the remaining channel. 2.5.9.2 analog loop-back (no. 3) loop-back #3 is invoked by sending c/i command arl to the u-transceiver. the loop is closed by the u-transceiver as near to the u-interface as possible. for this reason it is also called analog loop-back. all analog signals will still be passed on to the u-interface. as a result the opposite station (lt) is activated as well. in order to open an analog loop-back correctly, reset the u-transceiver into the test state with the c/i-command res. this ensures that the echo coefficients and equalizer coefficients will converge correctly when activating the following time.
psb 21911 psf 21911 u-transceiver semiconductor group 78 11.97 2.5.10 analog line port the analog part of the iec-q te consists of three main building blocks: C the analog-to-digital converter in the receive path C the digital-to-analog converter in the transmit path C the output buffer in the transmit path furthermore it contains some special functions. these are: C analog test loop-back C level detect function analog-to-digital converter the adc is a sigma-delta modulator of second order using a clock rate of 15.36-mhz. the peak input signal measured between ain and bin must be below 4 vpp. in case the signal input is too low (long range), the received signal is amplified internally by 6 db. the maximum signal to noise ratio is achieved with 1.3 vpp (long range) and 2.6 vpp (short range) input signal voltage. digital-to-analog converter the output pulse is shaped by a special dac. the dac was optimized for excellent matching between positive and negative pulses and high linearity. it uses a fully differential capacitor approach. the staircase-like output signal of the dac drives the output buffers. the shape of a dac-output signal is shown below, the peak amplitude is normalized to one. this signal is fed to an rc-lowpass of first order with a corner frequency of 1 mhz 50%. the duration of each pulse is 24 steps, with t0 = 0.78 m s per step. on the other hand, the pulse rate is 80-khz or one pulse per 16 steps. thus, the subsequent pulses are overlapping for a duration of 8 steps.
psb 21911 psf 21911 u-transceiver semiconductor group 79 11.97 figure 24 dac-output for a single pulse output stage the output stage consists of two identical buffers, operated in a differential mode. this concept allows an output-voltage swing of 6.4 vpp at the output pins of the iec-q te. the buffers are optimized for: C high output swing C high linearity C low quiescent current to minimize power consumption the output jitter produced by the transmitter (with jitter-free input signals) is below 0.02 uipp (unit intervall = 12.5 m s, peak-peak) measured with a high-pass filter of 30-hz cutoff frequency. without the filter the cutoff frequency is below 0.1 uipp. analog loop-back function the loop-back c/i command arl activates an internal, analog loop-back. this loop-back is closed near the u-interface. all signals received on ain / bin will neither be evaluated nor recognized after reaching the synchronized state in nt-mode. level detect the level detect circuit evaluates the differential signal between ain and bin. the differential threshold level is between 4 mv and 28 mv. the dc-level (common mode level) may be between 0 v and 3 v. level detect is not effected by the range setting.
psb 21911 psf 21911 u-transceiver semiconductor group 80 11.97 pulse shape the pulse mask for a single positive pulse measured between aout and bout at a load of 98 w is given in the following figure. figure 25 pulse mask for a single positive pulse hybrid the hybrid circuit for the iec-q te is shown on page 110.
psb 21911 psf 21911 access to iom-2 channels semiconductor group 81 11.97 2.6 access to iom-2 channels important : this chapter applies only in p mode in p mode the microcontroller has access to the iom-2 channels via the processor interface (pi) and registers. figure 26 access to iom-2 channels (p mode) the processor interface can be understood as an intelligent switch between iom-2 and the u-transceiver. it handles d, b1, b2, c/i and monitor-channel data. the data can either be transferred directly between iom-2 and the u-transceiver, or be controlled via the pi. the pi acts as an additional participant to the monitor channel. switching directions are selected by setting the register swst as indicated below: ? setting one of the 5 bits b1, b2, d, ci, or mon of swst to "1" enables the p access to the corresponding data. ? setting the bits listed above to "0" directly passes the corresponding data from iom-2 to the u-transceiver and vice versa. for a description of the bits wt, bs and sgl please refer to page 127 . the default value after hardware reset is "0" at all 8 positions. swst-register wt b1 b2 d ci mon bs sgl its10193 fsc pi u u r iom -2 - 2
psb 21911 psf 21911 access to iom-2 channels semiconductor group 82 11.97 2.6.1 b-channel access setting swst:b1 (b2) to "1" enables the microprocessor to access b1 (b2)-channel data between iom-2 and the u-transceiver. eight registers (see table 16 ) handle the transfer of data from iom-2 to the p, from the p to iom-2, from the p to u and from u to the p: every time b-channel bytes arrive, an interrupt ista:b1 or ista:b2 respectively is created. it is cleared after the corresponding registers have been read. ista:b1 is cleared after rb1u and rb1i have been read. ista:b2 is cleared after rb2i and rb2u have been read. after an interrupt the data in rb1u and rb1i is stable for 125s. 2.6.2 d-channel access setting swst:d to "1" enables the microprocessor to access d-channel data between the iom-2 and the u-interface. four registers (see table 17 ) handle the transfer of data from iom-2 to the p, from the p to iom-2, from the p to u and from u to the p. two 2-bit fifos of length 4 collect the incoming d-channel packets from iom and u. every fourth iom-frame they are full, an interrupt ista:d is generated and the contents table 16 b1/b2-channel data registers register function wb1u write b1-channel data to u-interface rb1u read b1-channel data from u-interface wb1i write b1-channel data to iom-2 rb1i read b1-channel data from iom-2 wb2u write b2-channel data to u-interface rb2u read b2-channel data from u-interface wb2i write b2-channel data to iom-2 rb2i read b2-channel data from iom-2 table 17 d-channel data registers register function dwu write d-channel data to u-interface dru read d-channel data from u-interface dwi write d-channel data to iom-2 dri read d-channel data from iom-2
psb 21911 psf 21911 access to iom-2 channels semiconductor group 83 11.97 of the fifos are parallely shifted to dru and dri respectively. dru and dri have to be read before the next interrupt ista:d can occur, otherwise 8 bits will be lost. dwu and dwi have to be loaded with data for 4 iom-frames. data in dwu and dwi is assumed to be valid at the time ista:d occurs. the register contents are shifted parallely into two 2-bit fifos of length four, from where the data is put to iom-2 and u respectively during the following 4 iom-frames. during this time, new data can be placed on dwu and dwi. dwu and dwi are not cleared after the data was passed to the fifos. that is, a byte may be put into dwu or dwi once and continously passed to iom or u, respectively. figure 27 illustrates this procedure: figure 27 procedure for the d-channel processing note: default of dwu, dwi, dru and dri after reset is "ff h ". 2.6.3 c/i channel access setting swst:ci to "1" enables the microprocessor to access c/i-commands and indications between iom-2 and the u-transceiver. a change in two consecutive frames (double last look) in the c/i-channel on iom-2 is indicated by an interrupt ista:cici. the received c/i-command can be read from register ciri. a change in the c/i-channel coming from the u-transceiver is indicated by an interrupt ista:cicu. the new c/i-indication can be read from register ciru . note: the term c/i-indication always refers to a c/i-code coming from the u-transceiver, whereas the term c/i-command refers to a c/i-code going into the u-transceiver. a c/i-code going to the u-transceiver has to be written into the ciwu-register. a c/i- code to iom-2 has to be written into the ciwi-register. the contents of both registers (ciwu and ciwi) will be transferred at the next available iom-2 frame. the registers are not cleared after the transfer. therefore, it is possible to continously send c/i codes to iom-2 or the u-transceiver by only writing the code into the register once.
psb 21911 psf 21911 access to iom-2 channels semiconductor group 84 11.97 c/i-commands to the u-transceiver have to be applied at least for two iom-2 frames (250 s) to be considered as valid. in te mode (i.e. 1.536 mhz dcl), the adf2:te1 bit is used to direct the c/i-channel access either to iom-2 channel 0 (adf2:te1 = 0, default) or to iom-2 channel 1 of the iom-2 terminal structure (adf2:te1 = 1), figure 28 on page 84 . this allows to program terminal devices such as the arcofi via the processor interface of the iec-q te. the c/i code going to iom-2 is 4 bits long if it is written to iom-2 channel 0 (adf2:te1 = 0). if written to iom-2 channel 1 this c/i code is 6 ibts long (adf2:te1 = 1). if the adf2:te1 bit is 1, the c/i channel on iom-2 channel 0 is passed transparently from the iom-2 interface to the iec-q te itself. figure 28 c/i channel access 2.6.4 monitor channel access setting swst:mon to "1" enables the microprocessor to access monitor-channel messages at iom-2 interface and the u-transceiver. monitor-channel access can be performed in three different iom-2 channels (see figure 29, page 85 ). itb10296 adf2 : te1 = 1 swst : ci = 1 iec-q core c/i access to iom -2 channel 1 r ciwu ciru ciwi ciri c/i 1 (6 bit) iom -2 r itb10295 adf2 : te1 = 0 swst : ci = 1 iec-q core c/i access to iom -2 channel 0 r ciwu ciru ciwi ciri c/i 0 (4 bit) iom -2 r (4 bit) c/i
psb 21911 psf 21911 access to iom-2 channels semiconductor group 85 11.97 figure 29 monitor channel access directions setting swst:mon to 0 disables the controller access to the monitor channel ( figure 29 upper left part). setting swst:mon to 1 enables three different ways of controller access to the monitor channel. adf2:te1 set to 0 allows to either access the u-transceiver core of the iec-q te (see figure 29 upper right part, adf2:min = 1) or the iom-2 interface of the iec-q te ( figure 29 lower left part, adf2:min = 0). setting adf2:te1 to 1 in te mode gives access to iom-2 channel 1 rather than iom-2 channel 0 directed out of the iec-q te. this allows to program devices linked to iom-2 channel 1 (e.g. arcofi) via the processor interface of the iec-q te. its10293 "din" "dout" iec-q core iec-q te p interface m swst : mon = 0 din dout dout din adf2 : te1 = 0 adf2 : min = 1 swst : mon = 1 m p interface iec-q te iec-q core "dout" "din" mode 1 : monitor channel access disabled to kernel "din" "dout" iec-q core iec-q te p interface m swst : mon = 1 adf2 : min = x adf2 : te1 = 1 din dout dout din adf2 : te1 = 0 adf2 : min = 0 swst : mon = 1 m p interface iec-q te iec-q core "dout" "din" to iom -2 mode 2 : monitor channel access mode 3b : monitor channel access mode 3a : monitor channel access to iom -2 channel 1 in te mode iom -2 channel 1 r r r iom -2 channel 0 r
psb 21911 psf 21911 access to iom-2 channels semiconductor group 86 11.97 2.6.4.1 monitor channel protocol the pi allows to program the iec-q te monitor channel in the way known from the peb 2070 icc. the monitor channel operates on an asynchronous basis. while data transfers on the iom-bus occur synchronized to frame sync fsc, the flow of data is controlled by a handshake procedure using the monitor channel receive (mr) and monitor channel transmit (mx) bits. for example: data is placed onto the monitor channel and the mx bit is activated. this data will be transmitted repeatedly once per 8-khz frame until the transfer is acknowledged via the mr bit. the microprocessor may either enforce a "1" (idle) in mr, mx by setting the control bit mocr:mrc or mocr:mxc to "0", or enable the control of these bits internally by the iec-q te according to the monitor channel protocol. thus, before a data exchange can begin, the control bits mrc or mxc should be set to "1" by the microprocessor. the monitor channel protocol is illustrated in figure 30 . the relevant control and status bits for transmission and reception are: monitor transmit bits register bit control / status function mocr mxc control mx bit control mxe transmit interrupt enable mosr mda status data acknowledged mab data abort star mac transmission active monitor receive bits register bit control / status function mocr mrc control mr bit control mre receive interrupt enable mosr mdr status data received mer end of reception
psb 21911 psf 21911 access to iom-2 channels semiconductor group 87 11.97 figure 30 monitor channel protocol before starting a transmission, the microprocessor should verify that the transmitter is inactive, i.e. that a possible previous transmission has been terminated. this is indicated by a "0" in mosr:mac, the monitor channel active status bit. to enable interrupts for the transmitter the mocr:mxe bit must be set to 1 (for details see section 4.1.1 on page 115 ). after having written the monitor data transmit (mox) register, the microprocessor sets the monitor transmit control bit mxc to "1". this enables the mx bit to go active (0), indicating the presence of valid monitor data (contents of mox) in the corresponding frame. as a result, the receiving device stores the monitor byte in its monitor receive (mor) register and generates an mdr interrupt status. alerted by the mdr interrupt, the microprocessor reads the monitor receive (mor)
psb 21911 psf 21911 access to iom-2 channels semiconductor group 88 11.97 register. when it is ready to accept data (e.g. based on the value in mor, which in a point-to-multipoint application might be the address of the destination device), it sets the mr control bit mrc to "1" to enable the receiver to store succeeding monitor channel bytes and acknowledge them according to the monitor channel protocol. in addition, it enables other monitor channel interrupts by setting monitor receive interrupt enable (mre) to "1". as a result, the first monitor byte is acknowledged by the receiving device setting the mr bit to "0". this causes a monitor data acknowledge (mda) interrupt status at the transmitter. a new monitor data byte can now be written by the microprocessor in mox. the mx bit is still in the active (0) state. the transmitter indicates a new byte in the monitor channel by returning the mx bit active after sending it once in the inactive state. as a result, the receiver stores the monitor byte in mor and generates a new mdr interrupt status. when the microprocessor has read the mor register, the receiver acknowledges the data by returning the mr bit active after sending it once in the inactive state. this in turn causes the transmitter to generate an mda interrupt status. this "mda interrupt C write data C mdr interrupt C read data C mda interrupt" handshake is repeated as long as the transmitter has data to send. note that the monitor channel protocol imposes no maximum reaction times to the microprocessor. when the last byte has been acknowledged by the receiver (mda interrupt status), the microprocessor sets the monitor transmit control bit (mxc) to "0". this enforces an inactive ("1") state in the mx bit. two frames of mx inactive signifies the end of a message. thus, a monitor channel end of reception (mer) interrupt status is generated by the receiver when the mx bit is received in the inactive state in two consecutive frames. as a result, the microprocessor sets the mr control bit mrc to 0, which in turn enforces an inactive state in the mr bit. this marks the end of the transmission, making the monitor channel active (mac) bit return to "0". during a transmission process, it is possible for the receiver to ask for a transmission to be aborted by sending an inactive mr bit value in two consecutive frames. this is effected by the microprocessor writing the mr control bit mrc to "0". an aborted transmission is indicated by a monitor channel data abort (mab) interrupt status at the transmitter. in te mode, the adf2:te1 bit is used to direct the monitor access either to iom-channel 0 (adf2:te1 = "0", default) or to iom-channel 1 of the iom-terminal structure. this allows to program terminal devices such as the arcofi via the processor interface of the iec-q te. if the adf2:te1 bit is "1", the monitor channel on iom-channel 0 is passed transparently from the iom-2 interface to the iec-q te itself.
psb 21911 psf 21911 s/g bit and bac bit in te mode semiconductor group 89 11.97 2.7 s/g bit and bac bit in te mode important : this chapter applies only in p mode and if dcl = 1.536 mhz (te mode). if dcl = 1.536 mhz the iom-2 interface consists of three iom-2 channels. the last octet of an iom-2 frame includes the s/g and the bac bit (chapter 2.3.1.1, page 31). either or both bits can be used in various applications including ? the d-channel arbitration in a pbx via an elic on the linecard ? the synchronization of a base station in radio in the local loop (rll) or wireless pbx applications the s/g is always written and never read by the iec-q te. its value depends on the last received eoc-command and on the status of the bac bit.the processing mode for the s/g bit is selected via bits swst:bs, swst:sgl and adf:cbac according to table 18 . a detailed description of the s/g bit in all modes is provided in appendix b . table 18 s/g processing mode swst: adf: description (x is dont care) application bs sgl cbac 0 0 x s/g bit always "0" (default) 0 1 0 s/g bit always "1" s/g and bac are handled by other devices than the iec-q te 0 1 1 s/g bit set to "1" continously with eoc 25 h received, reset to "0" with eoc 27 h received bac bit controlls s/g-bit, upstream d- channel not affected elic on linecard, interframe fill of terminals contains zeroes (e.g. 01111110) 1 0 x s/g bit set to "1" for 4 iom-frames with eoc 25 h receivced, automatically reset to "0" after that synchronizaiton of base station, e.g. ibmc or mbmc 1 1 0 s/g bit set to "1" continously with eoc 25 h receivced, reset to "0" with eoc 27 h received 1 1 1 s/g bit set to "1" continously with eoc 25 h receivced, reset to "0" with eoc 27 h received bac bit controlls s/g bit and upstream d- channel according to table 19 . elic on linecard, interframe fill of terminals are ones
psb 21911 psf 21911 s/g bit and bac bit in te mode semiconductor group 90 11.97 2.7.1 applications with elic on the linecard (pbx) the s/g bit on dout (downstream) and the bac bit on din (upstream) can be used to allow d-channel arbitration similar to the operation of the upn interface realised with the octat-p and the isac-p te. the basic function is as follows: the pbx linecard using the elic assigns one hdlc controller to a number of terminals. as soon as one terminal t requests the d-channel, e.g. for signalisation, all other terminals receive a message indicating the d-channel to be blocked for them. the request is done with the bac bit. at terminal t the bac bit is set and the iec-q te transfers the need for the d-channel to the lt-side. there, the hdlc-controller is assigned to the appropriate iom-channel. once this is done and indicated to the terminal by means of the s/g bit, the terminal begins to send d-channel messages. note that this procedure is somewhat different from the operation of the octat/isac- p te. there, the beginn of the upstream d-channel data transfer itself indicates the need for the hdlc-controller. this implies that any other terminal, that incidentally sent a hdlc-message the same time, can be stopped before the message is lost in case the hdlc-controller is not available. the u-interface featured by the iec-q te is not able to transfer the available/blocked information often enough to ensure this. hence, it is necessary to indicate a d-channel access by the terminal in advance. "in advance" actually means about 14 ms. giving mon-0 25 h at the lt during transparent operation will cause the d-channel access at the nt-side to be on "stop". as one eoc-message is transmitted via the eoc-channel once every 6 ms, the s/g bit on iom-2 can be set in 6 ms intervals. if the 4 channel lt chip set peb 24911 (dfe-q) is used in the lt, a peb 20550 (elic) can arbitrate the d-channel via the c/i command as known from the octat-p and quat-s devices. please refer to the peb 24911 data sheet for detailed information on this. the bac bit together with the eoc-messages received from the lt control the s/g bit and the upstream d-channel according to the table 19. table 19 control structure of the s/g bit and of the d-channel bac bit of last iom-frame s/g bit 1 = stop 0 = go d-channel upstream 0 reflects last received eoc message after falling edge after delay td1 (1.5 ms and two eoc- frames) tied to "0" 1 1 set transparent with first "0" in d- channel
psb 21911 psf 21911 s/g bit and bac bit in te mode semiconductor group 91 11.97 d-channel request by the terminal figure 31 illustrates the request for the hdlc-controller by the terminal. the start state is bac = 1 at din after td1 has expired. that causes the s/g bit to be set to the stop position. bac = 1 received on din sets the s/g bit on dout to the stop position ("1") at the next iom-frame. when the terminal requests access to the hdlc-controller in the elic it sets the bac-bit at din of its iec-q te to "0". that causes the d-channel data upstream to be tied to "0" and the s/g-bit to be set to "1". the elic receives the zeros and reacts by assigning the hdlc-controller to this very terminal. this is indicated via the change of c/ i code downstream at the lt side resulting in the s/g bit to be set to "0" (go) after delay td1 (see below for the explanation of td1 and td2). the iec-q te will continue to send "0" upstream in the d-channel until the actual hdlc data arrives at din.the hdlc-frame itself, marked by the first "0" in the d-channel will reset the d-channel back to transparent. this allows to have arbitrary delays between the s/g bit going to "0" and the d-channel being used without the risk of loosing the hdlc-controller by sending an abort request consisting of all "1". at the end of the hdlc-frame the bac bit is reset to "1" again by the layer-2 controller (e.g. smartlink; icc). this causes the s/g bit to be set to "1" in the next iom frame which stops a possible second hdlc-frame that could not be processed in the elic anymore. td1 and td2 the delays td1 and td2 (see figure 31 ) have the following reasons: td2 is caused by the 6ms interval in which an eoc message can be transmitted on the uko interface. as an eoc-message can start once every 6 ms and will take 6 ms to be transmitted, td2 will be 12 ms in the worst case. td1 is at minimum 7.5 ms depending on the location of the superframe at the time the hdlc-controller is requested by the terminal. this delay is necessary because instead of receiving an eoc-message "go" as requested, the terminal could as well receive the eoc message "stop" because the hdlc-controller was assigned to an other subscriber just before . flags as interframe fill the influence to the upstream d-channel can be disabled while the control of the s/g- bit via eoc-messages and via the bac bit still is given as described above by setting swst:bs to "0", swst:sgl to "1" and adf:cbac to "1". this is usefull when having a controlling device in the terminal, that is able to send the interframe timefill "flags".
psb 21911 psf 21911 s/g bit and bac bit in te mode semiconductor group 92 11.97 figure 31 d-channel request by the terminal itd10200 elic afe/dfe iec-q iec-q te te mode u k0 c/i = xxxx 1 = bac s/g = 1 d-channel transparent 1100 = c/i bac = 0 hdlc occupied by other terminal: d-channel fied to "0" delay td1 delay td2 "00" on d-channel eoc 25 h delay td2 hdlc assigned: c/i = 1000 h 27 eoc hdlc-controller available transparent; = s/g hdlc-frame on d-channel d-channel transparent frame hdlc bac = 1 eoc 25 h 1100 = c/i hdlc ready: delay td2 d-channel transparent 1; = s/g "stop" r iom -2 r r iom -2
psb 21911 psf 21911 reset semiconductor group 93 11.97 2.8 reset important : this chapter applies only in p mode. several resets are provided in the iec-q te. their effects are summarized in table 20 . the iom-2 clocks dcl and fsc as well as mclk are delivered during reset (except for power-on). the iec-q te provides a low active reset output (pin rst ) which is controlled by a power-on reset and the watchdog timer. the watchdog is enabled by setting the swst:wt bit to 1. default after hardware reset of swst:wt is "0". please refer to page 39 for information on how to use the watchdog timer. figure 32 illustrates the reset sources that have an impact on pin rst . figure 32 reset sources table 20 reset reset condition effect pin rst active power-on power-on resets the state machine and all registers yes hardware reset pin res = 0 resets the state machine and all registers exept for stcr register no watchdog watchdog expired resets no register and does not affect the state machine yes software reset c/i = 0001 resets the state machine and does not affect the registers no power-on
psb 21911 psf 21911 power controller interface semiconductor group 94 11.97 2.9 power controller interface important : this chapter applies only in stand-alone mode. a power controller interface is implemented in the psb 21911 to provide comfortable access to peripheral circuits which are not connected directly to the microprocessor . because this interface was specifically designed to support the isdn exchange power controller iepc (peb 2025) it is referred to as power controller interface. despite this dedication to the iepc, the controller interface is just as suited for other general-purpose applications. interface bits (pcd, pca, pcrd, pcwr, int) the interface structure is adapted to the register structure of the iepc. it consists of three data bits pcd0 ... 2, two address bits pca0,1, read and write signals pcrd and pcwr respectively as well as an interrupt facility int. the address bits are latched, they may therefore in general interface applications be used as output lines. for general interface inputs each of the three data bits is suitable. read and write operations are performed via mon-8 commands. three inputs and two outputs are thus available to connect external circuitry. the interrupt pin is edge sensitive. each change of level at the pin int will initiate a c/i- code int (0110 b ) lasting for four iom-frames. interpretation of the interrupt cause and resulting actions need to be performed by the control unit. table 21 lists all mon-8- and c/i-commands that are relevant to the power controller interface. table 21 mon-8 and c/i-commands channel code function mon-8 wci write to interface. address and data is contained in the mon- command. the address is latched, data is not latched. mon-8 rci read from interface at specified address. address is latched and the current value of the data port is read. the result is returned to the user with mon-8 aci. mon-8 aci answer from interface. after a rci-request the value of three data bits at the specified address is returned. c/i int interrupt. after a change of level has been observed, the c/i- code int is issued for 4 iom-frames. note the special timing of the interrupt signals described on page 96.
psb 21911 psf 21911 power controller interface semiconductor group 95 11.97 communication with the power controller interface is established with local monitor messages (mon-8) on iom-2. the following two-byte messages are matched to the iepc-power controller status register read and write operations but can be used in general, too. after the receipt of a mon-8-command the iec-q te will set the address/data bits and generate a read or write pulse. the address bits are latched, and the output is stable until it is overwritten by a new dedicated mon-8-command. all data lines are connected to an internal pull-up resistor. the initial value on the address lines after a soft or hardware reset is (11 b ). mon-8 wci write controller interface 10000000 011d0d1d2a0a1 mon-8 rci read controller interface 10000000 010CCCa0a1 mon-8 aci answer controller interface 10000000 d0d1d2CCCCC
psb 21911 psf 21911 power controller interface semiconductor group 96 11.97 interrupt for every change at the input pin int, the iec-q te will transmit a c/i-channel code (0110 b ), int, in 4 successive iom-2-frames. the input condition of the int pin is sampled every 4 iom-2-frames. an interrupt indication must therefore be applied to pin int for at least 4 iom-2-frames. figure 33 sampling of interrupts itd10294 125 m s 1ms ms 0.5 c/i code int int c/i code int int example a example b r iom -2 frames
psb 21911 psf 21911 c/i channel programming semiconductor group 97 11.97 3 operational description 3.1 c/i channel programming important : this chapter applies only in p mode. figure 34 example: c/i-channel use (all data values hexadecimal) itd10291 m p ciwu = c7 ista = 02 ciru = 03 cicu c/i channel handler transmit c/i- command "res" new c/i-code received from u read new c/i-code. c/i = 0000b = c/i = 0001b u-transceiver transfer to "test" state send c/i-indication "dr" interrupt
psb 21911 psf 21911 monitor channel programming semiconductor group 98 11.97 3.2 monitor channel programming important : this chapter applies only in p mode. the example on page 99 illustrates the read-out of the transceivers identification number (id). it consists of the transmission of a two-byte message from the control unit to the transceiver in iom channel 0. the transceiver acknowledges the receipt by returning a two-byte long message in the monitor channel. the procedure is absolutely identical for monitor channel 1. the m p starts the transfer procedure after having confirmed that the monitor channel is inactive. the first byte of monitor data is loaded into the transmit register mox. via the monitor control register mocr monitor interrupts are enabled and control of the mx-bit is handed over to the iec-q te. then transmission of the first byte begins. the u- transceiver reacts to a low level of the mx-bit by reading and acknowledging the monitor channel byte automatically. on detection of the confirmation, the iec-q te issues a monitor interrupt to inform the m p that the next byte may be sent. loading the second byte into the transmit register results in an immediate transmission (timing is controlled by iec-q te). the u-transceiver receives the second byte in the same manner as before. when transmission is completed, the u-transceiver sends end of message (mx-bit high). it is assumed that a monitor command was sent that needs to be answered by the u- transceiver (e.g. read-out of a register). therefore, the u-transceiver commences to issue a two-byte confirmation after an end-of-message indication from the iec-q te has been detected. the iec-q te notifies the m p via interrupt when new monitor data has been received. the processor may then read and acknowledge the byte at a convenient instant. when confirmation has been completed, the u-transceiver sends eom. this generates a corresponding interrupt in the iec-q te. by setting the mr-bit to high, the monitor channel is inactive, the transmission is finished.
psb 21911 psf 21911 monitor channel programming semiconductor group 99 11.97 example: monitor channel transmission and reception basic configuration, iom-2 clocks must be active w stcr = 0x15 // te mode, eoc auto mode w swst = 0x06 // access to c/i and monitor channel w adf2 = 0x48 // monitor access to u-transceiver transmission r mosr = 0x00 // transmission inactive (mac = 0) w mox = 0x80 // mon-8 command w mocr = 0x30 // transmit command r ista = 0x01 // monitor mda interrupt r mosr = 0x28 // ackn. indication w moxr = 0x00 // access to register 0 r ista = 0x01 // monitor mda interrupt r mosr = 0x28 // ackn. indication reception w mocr = 0x80 // enable receive of monitor message r ista = 0x08 // monitor mdr interrupt r mosr = 0x80 // data received r mor = 0x80 // value read monitor 8 command ind. w mocr = 0xc0 // acknowledge reading r ista = 0x08 // monitor mdr interrupt r mosr = 0x80 // data received r mor = 0x03 // data from register 0 (identification) r ista = 0x08 // monitor mdr interrupt r mosr = 0x40 // eom received w mocr = 0x80 // enable interrupts.
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 100 11.97 3.3 layer 1 activation/deactivation table 22 shows all u-interface signals as defined by ansi. table 22 u-interface signals notes: 1) alternating 3 symbols at 10 khz 2) must be generated by the exchange 3) alternating 3 single pulses of 12.5 m s duration spaced by 1.5 ms signal synch. word (sw) superframe (isw) 2b + d m-bits nt C> lt tn 1) 3 3 3 3 sn0 no signal no signal no signal no signal sn1 present absent 1 1 sn2 present absent 1 1 sn3 present present 1 normal sn3t present present normal normal lt C> nt tl 1) 3 3 3 3 sl0 no signal no signal no signal no signal sl1 present absent 1 1 sl2 present present 0 normal sl3 2) present present 0 normal sl3t present present normal normal test mode sp 3) no signal no signal 3 no signal
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 101 11.97 complete activation initiated by lt figure 35 depicts the procedure if the activation has been initiated by the exchange side. figure 35 complete activation initiated by lt itd10202 dc di dc di sl3t pu u-reference point sbcx iec-q te iec-q nt lt s/t arm act = 0 dea = 1 uoa = 1 0 info 0 info ar ar sl0 sn0 tl tn sn1 sn0 sl1 1 = uoa 1 = dea 0 = act sl2 sn2 0) (sai 0 = act sn3 = ai dc = sn3 act = 0 sai 1 sn3t sl3t ar ar ai ai info 3 info 2 4 info uai 1 sai 1 = act sn3 = 1 = uoa 1 = dea 1 = act sl3t r epic r iom -2 r iom -2
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 102 11.97 complete activation initiated by te figure 36 depicts the procedure if the activation has been initiated by the terminal side. figure 36 complete activation initiated by te itd04243 dc di dc di sl3t uoa = 1 uai u-reference point s/t arm info 0 info 0 ar sl0 sn0 tn sn1 sn0 sl1 sl2 act = 0 dea = 1 uoa = 0 sn2 sn3 sai = 1 dc info 1 tim pu ar ar r iom -2 r iom -2 sn3 act = 1 sai = 1 sl3t act = 1 dea = 1 uoa = 1 sn3t ai ai info 3 info 0 info 2 info 4 sbcx iec-q te iec-q epic nt lt r ai
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 103 11.97 complete deactivation figure 37 complete deactivation itd10204 ai ai ar ai sl3t sn3t dr di dc info 0 info 0 u-reference point sbcx iec-q te iec-q nt lt s/t dr di act = 1 dea = 1 uoa = 1 act = 1 sai = 1 0 = dea 0 = act sl3t 4 info 3 info dc deac 3ms ms 40 40 ms 3ms sl0 sn0 r iom -2 r iom -2 r epic
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 104 11.97 partial activation (u only) the iec-q te is in the synchronized 1 state (see state machine) after a successful partial activation. iom-2-clocks dcl and fsc are issued. on dout the c/i-message dc as well as the lt-user data is sent. while the c/i-messages di (1111 b ) or tim (0000 b ) are received on din, the iec-q te will transmit sai = (0) upstream. any other code results in sai = (1) to be sent. on the u-interface the signal sn3 (i.e. 2b + d = (1)) will be transmitted continuously regardless of the data on din. the lt will transmit all user data transparently downstream (signal sl3t). in case the last c/i-command applied to din was uar, the lt retains activation control when an activation request comes from the terminal (confirmation with c/i = ar required, see page 106 (case 1 ). with c/i dc applied on din, te initiated activations will be completed without the necessity of an exchange confirmation ( page 107 (case 2) ). figure 38 u only activation itd10205 dc di dc di sl3t pu uai u-reference point sbcx iec-q te iec-q nt lt s/t arm act = 0 dea = 1 uoa = 1 0 info 0 info ar uar sl0 sn0 tl tn sn1 sn0 sl1 0 = uoa 1 = dea 0 = act sl2 sn2 0 sai 0 = act sn3 = (dc) dc r epic r iom -2 r iom -2
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 105 11.97 activation initiated by lt with u active the s-interface is activated from the exchange with the command ar. bit uoa changes to (1) requesting s-interface activation. figure 39 lt initiated activation with u-interface active itd10206 dc di dc/uar uai sl3t sn3 ar ai ai info 3 info 2 ai u-reference point sbcx iec-q te iec-q nt lt s/t uai act = 0 dea = 1 uoa = 0 act = 0 sai = 0 1 = uoa 1 = dea 0 = act sl3t 1 = sai 1 = act sn3 sl3t act = 1 dea = 1 uoa = 1 0 info 0 info info 4 ar sn3t sl3t ar ar sn3 act = 0 sai = 1 r epic r iom -2 r iom -2
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 106 11.97 activation initiated by te with u active the te initiates complete activation with info 1 leading to sai = (1). case 1 requires the exchange side to acknowledge the te-activation by sending c/i = ar, case 2 activates completely without any lt-confirmation. figure 40 te-activation with u active and exchange control (case 1) itd10207 dc di uar uai sl3t sn3 ar ai ai info 3 info 2 ai u-reference point sbcx iec-q te iec-q nt lt s/t uai act = 0 dea = 1 uoa = 0 act = 0 sai = 0 1 = uoa 1 = dea 0 = act sl3t 1 = sai 1 = act sn3 sl3t act = 1 dea = 1 uoa = 1 0 info 0 info info 4 info 1 ar 1 = sai 0 = act sn3 sn3t sl3t ar ar r epic r iom -2 r iom -2
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 107 11.97 figure 41 te-activation with u active and no exchange control (case 2) itd10208 dc di dc uai sl3t sn3 ar ai ai info 3 info 2 ai u-reference point sbcx iec-q te iec-q nt lt s/t uai act = 0 dea =1 uoa = 0 act = 0 sai = 0 1 = uoa 1 = dea 0 = act sl3t 1 = sai 1 = act sn3 sl3t act = 1 dea =1 uoa =1 0 info 0 info info 4 info 1 ar 1 = sai 0 = act sn3 sn3t sl3t ar r epic r iom -2 r iom -2
psb 21911 psf 21911 layer 1 activation/deactivation semiconductor group 108 11.97 deactivating s/t-interface only deactivation of the s-interface only is initiated from the exchange by setting the uoa bit = (0). figure 42 deactivation of s/t only itd10209 ai ai ar ai sl3t sn3t dr di dc info 0 info 0 (dc) u-reference point sbcx iec-q te iec-q nt lt s/t uar uai act = 1 dea = 1 uoa = 1 act = 1 sai = 1 0 = uoa 1 = dea 1 = act sl3t 0 = sai 0 = act sn3 sl3t act = 0 dea = 1 uoa= 0 4 info 3 info r iom -2 r iom -2 r epic
psb 21911 psf 21911 external circuitry semiconductor group 109 11.97 3.4 external circuitry 3.4.1 power supply blocking recommendation the following blocking circuitry is suggested. figure 43 power supply blocking
psb 21911 psf 21911 external circuitry semiconductor group 110 11.97 3.4.2 u-interface the hybrid suggested for the psb 21911 iec-q te is identical to the hybrid recommended for the peb 2091 iec-q. figure 44 u-interface hybrid circuit note: to achieve optimum performance all capacitors of the hybrid should be mkt. ceramic capacitors are not recommended. its09706 3.01 k w 681 w 10 k w k 10 w 24 w w k 10 10 k w 24 w c k 6.8 nf 619 w 10 nf 10 nf 10 nf 1 m f 1:1.6 u 619 w aout bin ain bout _ <
psb 21911 psf 21911 external circuitry semiconductor group 111 11.97 3.4.3 oscillator circuit figure 45 illustrates the recommended oscillator circuit. a crystal or an oszillator signal may be used. figure 45 crystal oscillator or external clock source crystal parameters frequency: 15.36 mhz load capacitance: 20 pf +/- 0.3pf frequency tolerance: 60 ppm resonance resistance: 20 w max. shunt capacitance: 7 pf oszillator mode: fundamental external oscillator frequency: 15.36 mhz frequency tolerance: 80 ppm its09718 xout xin n.c. external oscillator signal 15.36 mhz 15.36 mhz 27 pf 27 pf xout xin
psb 21911 psf 21911 register description semiconductor group 112 11.97 4 register description important: this chapter applies only in p mode. the setting of the iec-q te in p mode and the transfer of data is programmed with registers. the address map and a register summary are given in table 23 and in table 24, respectively: table 23 register address map address (hex) read write name description name description 0 ista interrupt status register mask interrupt mask register 1 stcr status control register 2 mor read monitor data mox write monitor data 3 dru read d from u dwu write d to u 4 adf2 additional features reg. 2 5 reserved for the test mode (must not be used in normal operation) 6 rb1u read b1 from u wb1u write b1 to u 7 rb2u read b2 from u wb2u write b2 to u 8 rb1i read b1 from iom-2 wb1i write b1 to iom-2 9 rb2i read b2 from iom-2 wb2i write b2 to iom-2 a mosr monitor status register mocr monitor control register b dri read d from iom-2 dwi write d to iom-2 c ciru read c/i-code from u ciwu write c/i-code to u d ciri read c/i-code from iom-2 ciwi write c/i-code to iom-2 e adf additional features reg. f swst switch status register
psb 21911 psf 21911 register description semiconductor group 113 11.97 table 24 register summary add- ress 76543210name 0 h d cici cicu sf mdr b1 b2 mda ista r 0 h d cici cicu sf mdr b1 b2 mda mask w 1 h test1 test2 ms2 ms1 ms0 tm1 tm2 auto stcr w 2 h mor r 2 h mox w 3 h dru r 3 h dwu w 4 h te1 mto dod min adf2 w 6 h rb1u r 6 h wb1u w 7 h rb2u r 7 h wb2u w 8 h rb1i r 8 h wb1i w 9 h rb2i r 9 h wb2i w a h mdr mer mda mab mac mosr r a h mre mrc mxe mxc mocr w b h dri r b h dwi w c h 0 0 c/ic/ic/ic/i 1 1 ciru r c h 1 1 c/ic/ic/ic/i 1 1 ciwu w d h c/i c/i c/i c/i c/i c/i 1 1 ciri r d h c/i c/i c/i c/i c/i c/i 1 1 ciwi w e h wtc2 wtc1 pcl1 pcl0 bcl cbac adf w f h wt b1 b2 d ci mon bs sgl swst w
psb 21911 psf 21911 register description semiconductor group 114 11.97 4.1 interrupt structure the cause of an intrerrupt is determinded by reading the interrupt status register (ista). in this register, 7 interrupt sources can be directly read. interrupt bits are cleared by reading the corresponding registers. ista:d is cleared after dri and dru have been read. ista:b1 is cleared after rb1i and rb1u have been read. ista:b2 is cleared after rb2i and rb2u have been read etc. ista:cici is cleared after ciri is read, ista:cicu is cleared after ciru is read. ista:sf indicates a superframe marker received from the u-interface. it is cleared when the ista register has been read. pin int is set to "0" if one bit of ista changes from "0" to "1", except for the bit masked in the mask register. the mask register allows to prevent an interrupt to actually influence the int pin. setting the bits of mask that correspond to the bits of ista to "1" masks the bits, that is, the bits are still set in ista, but they do not contribute to the input of the nor-function on the interrupt bits which sets the int pin. the interrupt structure is illustrated in figure 46 : figure 46 interrupt structure
psb 21911 psf 21911 register description semiconductor group 115 11.97 4.1.1 monitor-channel interrupt logic the monitor data receive (mdr) and the monitor end of reception (mer) interrupt status bits have two enable bits, monitor receive interrupt enable (mre) and mr-bit control (mrc). the monitor channel data acknowledged (mda) and monitor channel data abort (mab) interrupt status bits have a common enable bit monitor interrupt enable (mxe). mre prevents the occurrence of the mdr status, including when the first byte of a packet is received. when mre is active ("1") but mrc is inactive, the mdr interrupt status is generated only for the first byte of a receive packet. when both mre and mrc are active, mdr is generated and all received monitor bytes - marked by a low edge in mx bit - are stored. additionally, an active mrc enables the control of the mr handshake bit according to the monitor channel protocol.
psb 21911 psf 21911 register description semiconductor group 116 11.97 4.2 registers ista-register read address 0 h the i nterrupt sta tus register (ista) generates an interrupt for the selected channel. interrupt bits are cleared by reading the corresponding register. default: 00 h 70 d cici cicu sf mdr b1 b2 mda 0 h d: d-channel interrupt d = 1 indicates an interrupt that 8 bits d-channel data have been updated. d = 0 occurs after dri and dru have been read. cici: c/i-channel interrupt cici = 1 indicates a change in the c/i-channel on iom-2. cici = 0 occurs after ciri is read. cicu: c/i-channel interrupt cicu = 1 indicates a change in the c/i-channel coming from the u-interface. cicu = 0 occurs after ciru is read. sf: superframe marker sf = 1 indicates a superframe marker received from the u- interface. sf = 0 occurs when the ista-register has been read. mdr: monitor data receive interrupt mdr = 1 indicates an interrupt after the mosr:mdr or the mosr:mer bits have been activated. mdr = 0 indicates the inactive interrupt status. b1: b1-channel interrupt b1 = 1 indicates an interrupt every time b1-channel bytes arrive. b1 = 0 occurs after rb1i and rb1u have been read.
psb 21911 psf 21911 register description semiconductor group 117 11.97 b2: b2-channel interrupt b2 = 1 indicates an interrupt every time b2-channel bytes arrive. b2 = 0 occurs after rb2i and rb2u have been read. mda: monitor data transmit interrupt mda = 1 indicates an interrupt after the mosr:mda or the mosr:mab bits have been activated. mda = 0 indicates the inactive interrupt status. mask-register write address 0 h the interrupt mask register (mask) can selectively mask each interrupt source in the ista register by setting to 1 the corresponding bit. default: ff h 70 d cici cicu sf mdr b1 b2 mda 0 h d: d-channel mask d = 1 prevents an interrupt ista:d to actually influence the int pin. d = 0 disables the function described above. cici: cici-channel mask cici = 1 prevents an interrupt ista:cici to actually influence the int pin. cici = 0 disables the function described above. cicu: cicu-channel mask cicu = 1 prevents an interrupt ista:cicu to actually influence the int pin. cicu = 0 disables the function described above. sf: superframe marker mask sf = 1 prevents an interrupt ista:sf to actually influence the int pin. sf = 0 disables the function described above.
psb 21911 psf 21911 register description semiconductor group 118 11.97 mdr: monitor data receive mask mdr = 1 prevents an interrupt ista:mdr to actually influence the int pin. mdr = 0 disables the function described above. b1: b1-channel mask b1 = 1 prevents an interrupt ista:b1 to actually influence the int pin. b1 = 0 disables the function described above. b2: b2-channel mask b2 = 1 prevents an interrupt ista:b2 to actually influence the int pin. b2 = 0 disables the function described above. mda: monitor data transmit mask mda = 1 prevents an interrupt ista:mda to actually influence the int pin. mda = 0 disables the function described above.
psb 21911 psf 21911 register description semiconductor group 119 11.97 stcr-register write address 1 h the st atus c ontrol r egister (stcr) selects the operating modes of the iec-q te as given in table. default: 04 h 70 0 0 ms2 ms1 ms0 tm1 tm2 auto 1 h bit 7: reserved set to 0 for future compatibility. bit 6: reserved set to 0 for future compatibility. ms2: mode selection 2 selects operation mode according to the table below. ms1: mode selection 2 selects operation mode according to the table below. ms0: mode selection 2 selects operation mode according to the table below. mode selection output pins u synchronized mode bit ms2 bit ms1 bit ms0 dcl out cls out super- frame- marker nt 0 0 0 512 7680 no nt 1 0 0 512 7680 yes nt-auto 0 0 1 512 7680 no te 0 1 0 1536 7680 no te 1 1 0 1536 7680 yes reserved others
psb 21911 psf 21911 register description semiconductor group 120 11.97 note: the stcr-register is only reset after a power-on. please refer also to table 20 on page 93. tm1: test-mode-bit 1 this bit determines, in combination with stcr:tm2, the operation modes. see table below. tm2: test-mode-bit 2 this bit determines, in combination with stcr:tm1, the operation modes. see table below. auto: selection between auto- and transparent mode auto = 1 sets the automode for eoc channel processing. auto = 0 sets the transparent mode for eoc channel processing. test-mode tm1 tm2 normal mode 1 0 send single-pulses 1 1 data-through 0 1
psb 21911 psf 21911 register description semiconductor group 121 11.97 adf2-register write address 4 h ad ditional f eatures register 2 (adf2). default: 08 h 70 te1 mto dod min 4 h te1: terminal equipment channel 1 te1 = 1 enables the iec-q te to write monitor data on dout to the mon1 channel instead of the mon0 channel and to write 6- bit c/i indications on dout into the c/i-channel 1. te1 = 0 enables the normal te operations where the iec-q te addresses only iom-2 channel 0. mto: monitor procedure timeout mto = 1 disables the internal 6ms monitor timeout. mto = 0 enables the internal 6ms monitor timeout. dod: dout open drain dod = 1 selects pin dout to be open drain. dod = 0 selects pin dout to be tristate. min: monitor-in-bit min = 1 combined with the swst:mon = 1 and adf2:te1 = 0 bits, enables the controller to access the core of the iec-q te. min = 0 combined with the swst:mon = 1 and adf2:te1 = 0 bits, enables the controller to access the iom-2 interface directed out of the iec-q te (see also page 85).
psb 21911 psf 21911 register description semiconductor group 122 11.97 mosr-register read address a h the mo nitor s tatus r egister (mosr) indicates the status of the monitor channel. default: 00 h 70 mdr mer mda mab mac a h mdr: monitor channel data received interrupt mdr = 1 generates an interrupt status after the receiving device has stored the contents of the mox register in the mor register. mdr = 0 inactive interrupt status mer: monitor channel end of reception interrupt mer = 1 is generated after two consecutive inactive mx bits (end of message) or as a result of a handshake procedure error. mer = 0 indicates that the transmission is running. mda: monitor channel data acknowledged mda = 1 results after a monitor byte is acknowledged by the receiving device. mda = 0 occurs when the receiver waits for an acknowledge of the monitor bit. mab: monitor channel data abort mab = 1 indicates that during a transmission the receiver aborted the process by sending an inactive (1) mr bit value in two consecutive frames. mab = 0 indicates that the transmission is running properly and that no abort request has been activated. mac: monitor channel active mac = 1 indicates a transmission on the monitor channel. mac = 0 indicates that the transmitter is inactive, i.e. ready for a transmission.
psb 21911 psf 21911 register description semiconductor group 123 11.97 mocr-register write address a h the mo nitor c ontrol r egister (mocr) allows to program and control the monitor channel as described in the section 4.1.1. default: 00 h 70 mre mrc mxe mxc a h mre: monitor receive interrupt enable mre = 1 enables the monitor data receive (mdr) interrupt status bit; mre = 1 enables the monitor data receive (mdr) and the monitor end of reception (mer) interrupt status bits. mre = 0 masks the mdr and the mer bits. mrc: monitor channel receive control mrc = 1 enables the control of the mr bit internally by the iec-q te according to the monitor channel protocol. mrc = 0 enforces a 1 (inactive state) in the monitor channel receive (mr) bit. mxe: monitor transmit interrupt enable mxe = 1 combined with the mxc bit tied to 1 enable the monitor channel data acknowledged (mda) and the monitor channel data abort (mab) interrupt status bits. mxe = 0 masks the mda and the mab bits. mxc: monitor channel transmit control mxc = 1 enables the control of the mx bit internally by the iec-q te according to the monitor channel protocol. mxc = 0 enforces a 1 (inactive state) in the monitor channel transmit (mx) bit.
psb 21911 psf 21911 register description semiconductor group 124 11.97 ciru-register read address c h the r ead c/i -code from u register (ciru) reads the c/i-code from the u-transceiver. default: 03 h 70 0 0 c/i c/i c/i c/i 1 1 c h 7., 6. bits: set to 0. 5.-2. bits: contain the c/i-indication coming from the u-transceiver. 1., 0. bits: set to 1. ciwu-register write address c h the w rite c/i -code to u register (ciwu) writes the c/i-code to the u-transceiver. default: c3 h 70 1 1 c/i c/i c/i c/i 1 1 c h 7., 6. bits: set to 1. 5.-2. bits: contain the c/i-code going to the u-transceiver. 1., 0. bits: set to 1.
psb 21911 psf 21911 register description semiconductor group 125 11.97 ciri-register read address d h the r ead c/i -code from i om-2 register (ciri) reads the c/i-code from the iom-2 interface. default: 03 h 70 c/i c/i c/i c/i c/i c/i 1 1 d h 7., 6. bits: adf2:te1 = 1 indicates that the c/i-channel 1 in the te mode can be accessed and that the c/i-channel on iom-channel 0 is passed transparently from the iec-q te to the iom-2. the two bits contain c/i-code. adf:te1 = 0 sets the normal mode. the two bits are set to 0. 5.-2. bits: contain the c/i-command coming from the iom-2. 1., 0. bits: set to 1. ciwi-register write address d h the w rite c/i -code to i om-2 register (ciwi) writes the c/i-code to the iom-2 interface. default: c7 h 70 c/i c/i c/i c/i c/i c/i 1 1 d h 7., 6. bits: these bits are the msbs of the 6-bit wide c/i code in iom-2 channel 1 if adf2:te1 = 1. if adf2:te1 = 0 these two bits have no effect. they should however be set to 1 for future compatibility. 5.-2. bits: contain the c/i-code going to the iom-2. 1., 0. bits: set to 1.
psb 21911 psf 21911 register description semiconductor group 126 11.97 adf-register write address e h ad ditional f eatures register (adf). default: 14 h 70 wtc2 wtc1 pcl1 pcl0 bcl cbac e h wtc2 , wtc1: watchdog controller the bit patterns 10 and 01 has to be written in wtc1 and wtc2 by the enabled watchdog timer within 132ms. if it fails to do so, a reset signal of 5ms at pin rst is generated. pcl1 , pcl0: prescaler the clock frequency on mclk is selected by setting the bits according to the table below: bit 2: reserved set to 0 for future compatibility. bcl: bit clock bcl = 1 changes the dcl-output into the bit-clock-mode. bcl = 0 gives the doubled bit clock on the dcl-output. cbac: control bac operates in combination with swst:sgl and swst:bs bits to control the s/g bit and the bac bit. for the functional description see table 18 on page 89 . pcl1 pcl0 frequency at mclk (mhz) 0 0 7.68 0 i 3.84 i 0 1.92 i i 0.96
psb 21911 psf 21911 register description semiconductor group 127 11.97 swst-register write address f h the sw itch st atus register (swst) selects the switching directions of the processor interface (pi). default: 00 h 70 wt b1 b2 d ci mon bs sgl f h wt: watchdog timer wt = 1 enables the watchdog timer (page 39). wt= 0 disables the watchdog timer. b1: b1-channel processing b1 = 1 enables the microprocessor to access b1-channel data between iom-2 and the u-interface. b1 = 0 disables the function described above. b2: b2-channel processing b2 = 1 enables the microprocessor to access b2-channel data between iom-2 and the u-interface. b2 = 0 disables the function described above. d: d-channel processing d = 1 enables the microprocessor to access d-channel data between iom-2 and u-interface. d = 0 disables the function described above. ci: c/i-channel processing ci = 1 enables the microprocessor to access c/i-commands and indications between iom-2 and u-interface. ci = 0 disables the function described above. mon: monitor-channel processing mon = 1 enables the microprocessor to access monitor-channel messages at iom-2 and at the u-interface. mon = 0 disables the function described above.
psb 21911 psf 21911 register description semiconductor group 128 11.97 bs: bs bit operates in combination with swst:sgl and adf:cbac bits to control the s/g bit and the bac bit. for the functional description see table 18 on page 89 . sgl: stop/go operates in combination with swst:bs and adf:cbac bits to control the s/g bit and the bac bit. for the functional description see table 18 on page 89 .
psb 21911 psf 21911 register description semiconductor group 129 11.97 b-channel access registers d-channel access registers monitor-channel access registers register value after reset (hex) function address (hex) wb1u 00 write b1-channel data to u-interface 6 rb1u 00 read b1-channel data from u-interface 6 wb1i 00 write b1-channel data to iom-2 8 rb1i 00 read b1-channel data from iom-2 8 wb2u 00 write b2-channel data to u-interface 7 rb2u 00 read b2-channel data from u-interface 7 wb2i 00 write b2-channel data to iom-2 9 rb2i 00 read b2-channel data from iom-2 9 register value after reset (hex) function address (hex) dwu ff write d-channel data to u-interface 3 dru ff read d-channel data from u-interface 3 dwi ff write d-channel data to iom-2 b dri ff read d-channel data from iom-2 b register value after reset (hex) function address (hex) mox ff monitor data transmit register 2 mor ff monitor data receive register 2
psb 21911 psf 21911 electrical characteristics semiconductor group 130 11.97 5 electrical characteristics 5.1 absolute maximum ratings note: stresses above those listed under absolute maximum ratings may cause permanent damage to the device. exposure to conditions beyond those indicated in the recommended operational conditions of this specification may affect device reliability. this is a stress rating only and functional operation of the device under those conditions or at any other condition beyond those indicated in the operational conditions of this specification is not implied. it is not implied, that more than one of those conditions can be applied simultaneously. parameter symbol limit values unit supply voltage v dd C 0.3 < v dd < 7.0 v input voltage v i C 0.3 < v i < v dd + 0.3 (max. 7) v output voltage v o C 0.3 < v o < v dd + 0.3 (max 7) v max. voltage applied at u-interface v s C 0.3 < v s < v dd + 0.3 (max. 7) v max. voltage between gnda1 (gnda2) and gndd v s 250 mv storage temperature t stg C 65 to 125 c ambient temperature psb 21911 psf 21911 t a t a 0 to 70 C 40 to 85 c c thermal resistance (system-air) (system-case) r th sa r th sc 40 9 k/w k/w
psb 21911 psf 21911 electrical characteristics semiconductor group 131 11.97 line overload protection the maximum input current (under overvoltage conditions) is given as a function of the width of a rectangular input current pulse as outlined in the following figure. figure 47 test condition for maximum input current u-transceiver input current the destruction limits for aout, bout, ain and bin are given in figure 48 . figure 48 u-transceiver input current itd09846 0.005 5 10 -9 -3 10 -1 10 1 s a wi t i 0.01 0.1 1
psb 21911 psf 21911 electrical characteristics semiconductor group 132 11.97 5.2 power consumption all measurements with random 2b + d data in active states. mode test conditions limit values unit typ. max. power up 5.00 v, open outputs 98 w load at aout/bout 53 59 ma nt-power down 5.00 v, open outputs 98 w load at aout/bout temperature 3 0 c 4.7 9 ma 5.00 v, open outputs 98 w load at aout/bout temperature < 0 c 6.5 11 ma
psb 21911 psf 21911 electrical characteristics semiconductor group 133 11.97 5.3 dc characteristics v dd = 4.75 to 5.25 v note: 1) inputs at vddd/gndd parameter symbol limit values unit test condition min. max. h-level input voltage v ih 2.0 v dd + 0.3 v l-level input voltage v il 0.8 v l-level input leakage current for all pins except for pin #11, #14, #15 i il C 10 m a v i = gndd 1) h-level input leakage current for all pins except for pin #11, #14, #15 i ih 10 m a v i = vddd 1) l-level input leakage current of pin #11 (xin) i il C 40 m a v i = gndd 1) h-level input leakage current of pin #11 (xin) i ih 40 m a v i = vddd 1) l-level input leakage current of pin #14, #15 (ain, bin) i il C 70 m a v i = gndd 1) h-level input leakage current of pin #14, #15 (ain, bin) i ih 70 m a v i = vddd 1) l-level input leakage current for pins with pull-up resistors i ilpu C 100 100 m a v i = gndd 1) h-level input leakage current for pins with pull-up resistors i ihpu C 10 10 m a v i = vddd 1) l-level input leakage current for pins with pull-down resistors i ilpd C 30 30 m a v i = gndd 1) h-level input leakage current for pins with pull-down resistors i ihpd 500 m a v i = vddd 1) h-level output voltage for all outputs except dout v oh1 2.4 v i oh1 = 0.4 ma 1) h-level output voltage for dout v oh2 3.5 v i oh2 = 6 ma 1) l-level output voltage for all outputs except dout v ol1 0.4 v i ol1 = 2 ma 1) l-level output voltage for dout v ol2 0.5 v i ol1 = 7 ma 1) input capacitance din, ps1, ps2, dcl, fsc (input) dout (open) c in 10 pf
psb 21911 psf 21911 electrical characteristics semiconductor group 134 11.97 note: 1) test conditions: 1.3 vpp antisemetric sine wave as input on ain/bin with long range (low, critical range). 2) interpretation and test conditions: the sum of noise and total harmonic distortion, weighted with a low pass filter 0 to 80 khz, is at least 65 db below the signal for an evenly distributed but otherwise random sequence of + 3, + 1, C 1, C 3. 3) the signal amplitude measured over a period of 1 min. varies less than 1%. 4) the percentage of the 1-values in the pdm-signal. pin capacitances u-transceiver characteristics limit values min. typ. max. unit receive path signal / (noise + total harmonic distortion) 1) 60 65 db dc-level at ad-output 45 50 55 % 4) threshold of level detect 4 20 28 mv input impedance ain/bin 50 k w transmit path signal / (noise + total harmonic distortion) 2) 65 70 db output dc-level 2.05 2.375 2.6 db offset between aout and bout 35.5 mv signal amplitude 3) 3.10 3.20 3.30 v output impedance aout/bout: power-up power-down 2 6 4 12 w w t a = 25 c; v dd = 5 v 5 %; v ss = 0 v; f c = 1 mhz pin parameter symbol limit values unit min. max. all pins except xin, xout pin capacitance c io 7pf xin, xout pin capacitance c io 5pf
psb 21911 psf 21911 electrical characteristics semiconductor group 135 11.97 supply voltages vdd d = + 5 v 0.25 v vdd a 1-2 = + 5 v 0.25 v the maximum sinusoidal ripple on vdd a 1-2 is specified in the following figure: figure 49 maximum sinusoidal ripple on supply voltage
psb 21911 psf 21911 electrical characteristics semiconductor group 136 11.97 5.4 ac characteristics t a = 0 to 70 c, v dd = 5 v 5% inputs are driven to 2.4 v for a logical "1" and to 0.4 v for a logical "0". timing measurements are made at 2.0 v for a logical "1" and 0.8 v for a logical "0". the ac testing input/output waveforms are shown in figure 50. figure 50 input/output waveform for ac tests 5.4.1 parallel microprocessor interface timing siemens/intel bus mode figure 51 siemens/intel read cycle
psb 21911 psf 21911 electrical characteristics semiconductor group 137 11.97 figure 52 siemens/intel write cycle figure 53 siemens/intel multiplexed address timing figure 54 siemens/intel non-multiplexed address timing
psb 21911 psf 21911 electrical characteristics semiconductor group 138 11.97 motorola bus mode figure 55 motorola read timing figure 56 motorola write cycle figure 57 motorola non-multiplexed address timing
psb 21911 psf 21911 electrical characteristics semiconductor group 139 11.97 microprocessor interface timing c load = 50pf parameter symbol limit values unit min. max. ale pulse width t aa 60 ns address setup time to ale t al 20 ns address hold time from ale t la 10 ns address latch setup time to wr , rd t als 0ns address setup time t as 35 ns address hold time t ah 0ns ale guard time t ad 70 ns ds delay after r/w setup t dsd 0ns rd pulse width t rr 280 ns data output delay from rd t rd 280 ns data float from rd t df 25 ns rd control interval t ri 70 ns w pulse width t ww 280 ns data setup time to w x cs t dw 170 ns data hold time w x cs t wd 10 ns w control interval t wi 70 ns
psb 21911 psf 21911 electrical characteristics semiconductor group 140 11.97 5.4.2 serial microprocessor interface timing the following 2 figures describe the read/write cycles and the corresponding address timing for the serial microprocessor interface: figure 58 serial p interface mode write figure 59 serial p interface mode read 1 a3 a2 a1 a0 x d7 x x d6 d5 d4 d3 d2 d1d0 css t p t cdins t cs cclk cdin cdout high z cdinh t csh t 0 a3 a2 a1 a0 x d7 xx d6 d5 d4 d3 d2 d1d0 cdin cdout high z cdoutd t css t p t cs cclk csh t
psb 21911 psf 21911 electrical characteristics semiconductor group 141 11.97 table 25 timing characteristics (serial p interface mode) c load = 50pf parameter symbol min. max. unit clock period t p 130 ns chip select setup time t css 0ns chip select hold time t csh 20 ns cdin setup time t cdins 40 ns cdin hold time t cdinh 40 ns cdout data out delay t cdoutd 30 ns
psb 21911 psf 21911 electrical characteristics semiconductor group 142 11.97 5.4.3 iom ? -2 interface timing 5.4.3.1 nt mode figure 60 iom ? -2 timing in nt mode itt10210 t wh t dcl wl t ddc t t ddf t wfh df t t hd sd t dcl fsc dout din data valid data valid t f t r
psb 21911 psf 21911 electrical characteristics semiconductor group 143 11.97 table 26 iom ? -2 in nt mode notes: 1) 256 kbit/s (dcl = 512 khz) 2) 768 kbit/s (dcl = 1.523 mhz) 3) the point of time at which the output data will be valid is referred to the rising edges of either fsc ( t ddf ) or dcl ( t ddc ). the rising edge of the signal appearing last (normally dcl) shall be the reference. 4) fsc marking superframe 5) fsc marking non-superframe parameter signal symbol limit values unit test condition min. typ. max. data clock rise/fall dcl t r , t f 30 ns c l = 25 pf clock period 1) t dcl 1875 1953 2035 ns c l = 25 pf pulse width 1) high/low t wh t wl 850 960 1105 ns clock period 2) t dcl 565 651 735 ns c l = 25 pf pulse width 2) high/low t wh t wl 200 310 420 ns frame width high 4) fsc t wfh t dcl c l = 25 pf frame width high 5) fsc t wfh 2 t dcl c l = 25 pf frame synch. rise/ fall t r , t f 30 ns c l = 25 pf frame advance t df 0 65 130 ns c l = 25 pf data out dout t f 200 ns c l = 150 pf ( r = 1 k w to v dd , open drain) data out t r , t f 150 ns c l = 150 pf (tristate) data delay clock 3) t ddc 100 ns c l = 150 pf data delay frame 3) t ddf 150 ns c l = 150 pf data sample delay din t sd t wh + 20 ns data hold t hd 50 ns
psb 21911 psf 21911 electrical characteristics semiconductor group 144 11.97 power controller interface (stand-alone mode only) figures 61 and 62 depict the timing for read and write operations. figure 61 dynamic characteristics of power controller write access figure 62 dynamic characteristics of power controller read access
psb 21911 psf 21911 electrical characteristics semiconductor group 145 11.97 table 27 power controller interface dynamic characteristics c load = 25pf parameter signal symbol limit values unit min. typ. max. write clock rise/fall pcwr t r, t f 30 ns write with low t wrl 4 t dcl ns address set-up pca0 1 t sad 2 t dcl ns data delay write pcd0 2 t ddw 2 t dcl ns data delay read t ddr 130 ns set-up data read t sdr 130 ns read clock rise/fall pcrd t r, t f 30 ns read width t rdl 4 t dcl ns
psb 21911 psf 21911 electrical characteristics semiconductor group 146 11.97 reset figure 63 reset signal table 28 reset timing parameter symbol limit values unit test conditions min. power-on reset active low state t rst 67 ms watchdog reset active low state t rst 5ms reset at pin res active low state t rst 10 ns t rst rst itd09823
psb 21911 psf 21911 package outlines semiconductor group 147 11.97 6 package outlines plastic package, p-lcc-44 (metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
psb 21911 psf 21911 package outlines semiconductor group 148 11.97 plastic package, t-qfp-64 (thin quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device
psb 21911 psf 21911 external component sourcing semiconductor group 149 11.97 7 external component sourcing the following tables contain transformers and crystals recommended by different manufacturers for use with siemens ics. no manufacturer can be recommended over another. transformers marked with * ) have been tested at siemens semiconductors and have shown positive test results. this list is not complete. it contains a few examples of devices offered by different manufacturers. most manufacturers offer a variety of components with different parameters. for latest information please contact the manufacturers directly or visit their web pages where available. note: there may also exist other manufacturers than those included in the list. table 29 u-transformer information part number comments contacts (phone) fax apc www.apcisdn.com apc42954 2kv, rm8, pth eu: +44 1634 2905-88 sea: +852 2410-2731 us: (201) 368 17-50 -91 -2518 -04 apc42963s 2kv, rm6, smd apc131... incl. hybrid and mlt p u l s e e n g i n e e r i n g www.pulse.com pe-65575 2kv eu: +44 14834-28877 sea: +886 78-213141 us: (619) 674 8100 -16011 -419707 -8262 pe-68669 3kv, reinforced pe-68670 3kv, low bit error rate s+m components www.siemens.de/pr v409 2kv, rm6, smd eu: +49 89 6362 4265 sea: +65 744-7768 us: (908)-906 4300 -6992 -632 2830 v832 2kv, rm8, pth w144 4kv, rm8, pth schott corporation us: (615)-889-8800
psb 21911 psf 21911 external component sourcing semiconductor group 150 11.97 vacuumschmelze www.vacuumschmelze.de t60403 -m6290-x054 2kv eu: +49 6181 38-2673 sea: +65 84-04 880 us: (405) 943 9651 -2780 -26 607 -949 2967 -m6290-x058 2kv/4kv; low bit error rate -m6276-x... 2kv; smd tdk eu: +49 2192 487-0 valor www.valorinc.com eu: +44 1727-8248-75 sea: +852 2 953-1000 us: (619) 537-2500 -98 -1333 -2525 vogt www.vogt-electronic.com 544 03 006 00 2kv, pth eu: +49 8591 17-0 sea: +86 21 6251-2227 us: (914) 921-6900 -240 -4489 -6381 table 29 u-transformer information (contd) part number comments contacts (phone) fax
psb 21911 psf 21911 external component sourcing semiconductor group 151 11.97 table 30 crystal information part number comments contacts (phone) fax frischer electronic eu: +49 9131-33007 kvg eu: +49 7263 648-0 ndk j: (03)-460-2111 us: (408) 255-0831 saronix us: (415) 856-6900 tele quarz eu: +49 7268 8010
psb 21911 psf 21911 glossary semiconductor group 152 11.97 8 glossary a/d analog-to digital adc analog-to digital converter agc automatic gain control ain differential u-interface input ansi american national standardization institute arcofi audio ringing codec filter aout differential u-interface output b 64-kbit/s voice and data transmission channel bcl bit clock bin differential u-interface input bout differential u-interface output c/i command/indicate (channel) ccitt comit consultatif international des tlphones et tlgraph ccrc corrupted crc crc cyclic redundancy check d 16-kbit/s data and control transmission channel d/a digital-to-analog dac digital-to-analog converter dcl data clock dd data downstream dt data through test mode du data upstream ec echo canceller eoc embedded operations channel eom end of message etsi european telephone standards institute febe far-end block error fifo first-in first-out (memory) fsc frame synchronizing clock gnd ground hdlc high-level data link control icc isdn-communications controller iec-q isdn-echo cancellation circuit conforming to 2b1q-transmission code iom-2 isdn-oriented modular 2nd generation info u- and s-interface signal as specified by ansi/etsi isdn integrated services digital network isw inverted synchronization word lb loop back lbbd loop-back of b- and d-channels lsb least significant bit lt line termination mon monitor channel command msb most significant bit mr monitor read bit mto monitor procedure timeout mx monitor transmit bit
psb 21911 psf 21911 glossary semiconductor group 153 11.97 ncc notify of corrupt crc nebe near-end block error nt network termination osi open systems interconnection pll phase locked loop ps power supply status bit psd power spectral density ptt post, telephone, and telegraph administration pu power-up rcc request corrupt crc rci read power controller interface rms root mean square rp repeater s/t two-wire pair interface sbcx s/t-bus interface circuit extended sicofi signal processing codec filter slic subscriber line interface circuit ssp send single pulses (test mode) st self test sw synchronization word te terminal equipment tl wake-up tone, lt side tn wake-up tone, nt side tp test pin u single wire pair interface utc unable to comply 2b1q transmission code requiring 80-khz bandwidth
semiconductor group 154 11.97 psb 21911 psf 21911 appendix appendix a: jitter on iom-2 the output jitter on the iom-2 clocks fsc and dcl/bcl may be higher than in versions 4.3 and older. the jitter on pin cls is the same as in versions 4.3 and older. this does not contradict any norm or specification. however in jitter sensitive applications the system performance should be rechecked. for pcm-2 applications - as depicted in the iec-q v4.3 users manual 02.95 on page 44 - it is not recommended to use the iec-q te v5.2 together with version 3.0 of sicofi-2 (peb/f 2260). this is due to the somewhat different behavior of this sicofi-2 version from earlier versions (see delta sheet, may 1996, of the peb/f 2260). instead, it is recommended to use the peb 2091 iec-q in nt-pbx mode for pcm-2 applications with the peb/f 2260. the application with iec-q and sicofi-2 is described in the iec-q v5.2 errata sheet 09.97 on page 6ff.
semiconductor group 155 11.97 psb 21911 psf 21911 appendix appendix b:s/g bit control state machine the state machine of the s/g bit control in te mode is given in the following state diagrams. the values in the state diagrams are to be interpreted as follows: figure 64 s/g bit state machine notation state n am e o utput value state n um ber input value input value
semiconductor group 156 11.97 psb 21911 psf 21911 appendix figure 65 state machine (part 1) reset d0=0;sg=z 1 pmode = 0 or act = 0 or te = 0 s/g to 0 d0=0;sg=0 2 s/g to 1 d0=0;sg=1 3 (pmode=act=te=1) and (bs=cbac=0) and (sgl=1) s/g-4t to 0 d0=0;sg=0 4 bs=1 and sgl=0 s/g-4t to 1 d0=0;sg=1 5 s/g transp. d0=0;sg=z 6 s/g transp. 1 d0=0;sg=1 7 eoc=25 (bs=sgl=1) s/g transp. 0 d0=0;sg=0 8 eoc=27 eoc=27 eoc=25 1 1 (pmode=act=te=1) and (bs=sgl=0) eoc=25 t4 set t4 expired and cbac=0
semiconductor group 157 11.97 psb 21911 psf 21911 appendix figure 66 state machine (part 2) hdlc ctrl d0=0;sg=1 8 bac-edge d0=0;sg=1 9 bac=0 td1 set wait for eoc d0=0;sg=1 10 td1 expired s/g go d0=0;sg=0 12 s/g stop d0=0;sg=1 13 eoc=27 eoc=25 (pmode=act=te=1) and (sgl=cbac=1) and (bs=0) and (bac=1) eoc=27 eoc=25
semiconductor group 158 11.97 psb 21911 psf 21911 appendix figure 67 state machine (part 3) hdlc ctrl d0=0;sg=1 14 bac-edge d0=1;sg=1 15 wait for eoc d0=1;sg=1 17 s/g go d0=1;sg=0 18 s/g stop d=1;sg=1 19 hdlc-f go d0=0;sg=0 20 hdlc-f stop d0=0;sg=1 21 (pmode=act=te=1) and (bs=sgl=cbac=1) and (bac=1) bac=0 td1 set td1 expired eoc=27 eoc=25 eoc=27 eoc=25 hdlc_frame hdlc_frame eoc=25 eoc=27
semiconductor group 159 11.97 psb 21911 psf 21911 appendix table 31 state machine input signals no. signal name description 1 pmode corresponds to the pmode pin. set to "1" (only) in the microprocessor mode 2 te this input is set to "1" (only) in the te mode 3 act "1" on this input indicates receiver synchronization (e.g. in the transparent state, see iec-q v4.3 users manual 02.95, page 175). 4 bs swst:bs bit. 5 sgl swst:sgl bit. 6 cbac adf:cbac bit. 7 eoc=25 this input indicates that the eoc code 25h (stop) was received on the u interface. 8 eoc=27 this input indicates that the eoc code 27h (go) was received on the u interface. 9 t1 set a 500 micro seconds timer is enabled. 10 t1 expired the 500 micro seconds timer (see 9) has expired. 11 td1 set the timer td1 is enabled. this timer depends on the position of the eoc frame in the currently received u data. it varies between 7.5 and 15 ms. 12 td1 expired the timer td1 has expired. this timer depends on the position of the eoc frame in the currently received u data. it varies between 7.5 and 15 ms. 13 bac bac bit on din. this is bit no. 27 positioned in the third iom slot table 32 state machine output signals no. signal name description 1 sg value of the s/g bit on dout. the s/g bit is bit no. 27 in the third slot on dout. sg=z means that the sg bit has the value high z 2 d0 sets the d channel upstream to "0" if active ("1")
semiconductor group 160 11.97 psb 21911 psf 21911 appendix appendix c:quick reference guide this chapter contains tables and figures often required when working with the psb 21911. for additional technical information please refer to the relevant chapter.
semiconductor group 161 11.97 psb 21911 psf 21911 appendix u-transceiver state diagram figure 68 u-transceiver state diagram itd09705 any state pin-dt or dt any state pin-ssp or pin-res or ssp or res dc deactivated . 0 sn sn0 . iom pu dc alerting . tn sn1 . ec-training dc sn0 . eq-training dc sn2 . wait for sf dc dc synchronized 1 sn3/sn3t ar/arl ar/arl wait for act ai/ail transparent sn3t ar/arl error s/t sn0 . pending timing dc ar analog loop back dc wait for sf al 3 sn dc ec-training al . 1 sn sn0/sp . test dr dr ec-training 1 . 1 sn tn . alerting dr dr pend. deact. s/t 3 sn sn0 . pend. receive res. ei1 pend. deact. u dc dr receive reset . 0 sn ar or tl tim or din = 0 t14 s t14 e tl t14 s t11s t1s, t12s t11e pu lsec or t12e bbd0 & fd lsue or t1e t1e lof bbd0 & sfd act = 0 uoa = 1 act = 0 synchronized 2 uoa = 0 lsue dea = 0 dea = 0 lsue lof lof act = 1 ei1 lof act = 1 sn3t act = 0 ei 1 uoa = 0 dea = 0 lsue lsue dea = 0 uoa = 0 uoa = 0 dea = 0 lsue act = 1 act = 0 ai act = 0 lof act = 1 & ai di di t11e t12s (lsec or t12e) & di 1 lof di lsue dea = 0 act = 1/0 lsu act = 1 sn3t dea = 1 uoa = 1 ? no yes & t13e) lsu or (/lof t13s t7s tl t7s & di t7e act = 0 act = 0 sn3t arl bbd1 & sfd t14 s di awaked ar or tl di t1s, t11s t11s t1s, lsec or t12e t12s sn3/sn3t sn3/sn3t r
semiconductor group 162 11.97 psb 21911 psf 21911 appendix table 33 u-transceiver c/i codes code nt-mode in out 0000 tim dr 0001 res C 0010 C C 0011 C C 0100 ei1 ei1 0101 ssp C 0110 dt int 0111 C pu 1000 ar ar 1001 C C 1010 arl arl 1011 C C 1100 ai ai 1101 C C 1110 C ail 1111 di dc ai activation indication ei1 error indication 1 ar activation request int interrupt arl activation request local loop pu power-up dc deactivation confirmation res reset di deactivation indication ssp send-single-pulses test mode dr deactivation request tim timing request dt data-through test mode
semiconductor group 163 11.97 psb 21911 psf 21911 index a absolute maximum ratings 130 ac characteristics 136 activation/deactivation examples 100 analog line port 78 auto mode (eoc) 51 b bac bit and s/g bit 89 b-channel access 82 block error counters 46 blocking capacitors 109 c c/ i channel 34 c/i channel example 97 c/i codes 75, 162 c/i-channel access 83 cold start 63 component sourcing 149 crystal suppliers 151 cyclic redundancy check 44 d dc characteristics 133 d-channel access 82 device architecture 28 dout driver modes 27 e electrical characteristics 130 elic 90 embedded operations channel 50 eoc 50 eoc-processor 51 external circuitry 109 f features 9 g glossary 152 h hybrid 110 i interrupt structure 114 iom-2 30 iom-2 clocks 37 iom-2 output driver 38 iom-2 channel access 81 iom-2 jitter 154 j jitter 154 l layer 1 loop-backs 76 line overload protection 131 local functions 59 logic symbol p 10 logic symbol nt1 11 loop-back 76 loop-back (no. 2) 76 loop-back (no. 3) 77 m microprocessor bus selection 39 microprocessor clock output 39 microprocessor interface 21 mon-0 51 mon-1 54 mon-2 56 mon-8 59 monitor channel 35 access 84 interrupt 115 programming example 98 protocol 86 timeout 36 o operating modes 26 oscillator circuit 111 overhead bits 56 p package outlines 147 partial activation 104 pbx linecard 90
semiconductor group 164 11.97 psb 21911 psf 21911 index pin configuration 12 pin definitions 13 power consumption 132 power controller interface 94 power supply 109 pulse shape 80 q quick reference guide 160 r register address map 112 register summary 113 reset 93 reset timing 146 s s/g bit and bac bit 89 scrambler / descrambler 49 state diagram 64, 161 state machine notation rules 62 superframe marker 38 system integration 22 t test modes 27 transformer suppliers 149 transparent mode (eoc) 51 u u-interface hybrid 110 u-interface signals 100 u-transceiver 40 block diagram 41 frame structure 42 state machine 63, 161 w warm start 63 watchdog timer 39

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